Showing papers on "Stuck-at fault published in 2009"

Fault Location on Power Networks

Abstract: Electric power systems will always be exposed to the failure of their components. When a fault occurs on a line, it is crucial for the fault location to be identified as accurately as possible, allowing the damage caused by the fault to be repaired quickly before the line is put back into service. Fault Location on Power Lines enables readers to pinpoint the location of a fault on power lines following a disturbance. If a fault location cannot be identified quickly and this causes prolonged line outage during a period of peak load, severe economic losses may occur and reliability of service may be questioned. The growth in size and complexity of power systems has increased the impact of failure to locate a fault and therefore heightened the importance of fault location research studies, attracting widespread attention among researchers in recent years. Fault location cannot be truly understood, applied, set, tested and analysed without a deep and detailed knowledge of the interiors of fault locators. Consequently, the nine chapters are organised according to the design of different locators. The authors do not simply refer the reader to manufacturers documentation, but instead have compiled detailed information to allow for in-depth comparison. Fault Location on Power Lines describes basic algorithms used in fault locators, focusing on fault location on overhead transmission lines, but also covering fault location in distribution networks. An application of artificial intelligence in this field is also presented, to help the reader to understand all aspects of fault location on overhead lines, including both the design and application standpoints. Professional engineers, researchers, and postgraduate and undergraduate students will find Fault Location on Power Lines a valuable resource, which enables them to reproduce complete algorithms of digital fault locators in their basic forms.

Robust Fault Detection for Switched Linear Systems With State Delays

Abstract: This correspondence deals with the problem of robust fault detection for discrete-time switched systems with state delays under an arbitrary switching signal. The fault detection filter is used as the residual generator, in which the filter parameters are dependent on the system mode. Attention is focused on designing the robust fault detection filter such that, for unknown inputs, control inputs, and model uncertainties, the estimation error between the residuals and faults is minimized. The problem of robust fault detection is converted into an H infin-filtering problem. By a switched Lyapunov functional approach, a sufficient condition for the solvability of this problem is established in terms of linear matrix inequalities. A numerical example is provided to demonstrate the effectiveness of the proposed method.

Extended Operation of Cascade Multicell Converters Under Fault Condition

Abstract: Multilevel converters are an interesting alternative for high power drives, due to their good quality output signals. Despite their advantages, the large number of components required increases the fault probability. Among the multilevel topologies, the cascade multicell converter presents advantages when operating under internal fault conditions, due to its high modularity. Previous works proposed to compensate the unbalanced operation due to a fault by changing the canonical fundamental output phase shift to precalculated angles, depending on the fault condition. This solution assumes that, if the maximum output phase voltage on each leg is used, the maximum line-to-line voltage will be at a maximum as well. This paper shows how this assumption is not always valid and presents the optimum angles and modulation indexes that must be used in order to obtain the maximum balanced load voltages.

Incipient Bearing Fault Detection via Motor Stator Current Noise Cancellation Using Wiener Filter

Abstract: Current-based monitoring can offer significant economic savings and implementation advantages over traditional vibration monitoring for bearing fault detection. The key issue in current-based bearing fault detection is to extract bearing fault signatures from the motor stator current. Since the bearing fault signature in the stator current is typically very subtle, particularly when the fault is at an incipient stage, it is difficult to detect the fault signature directly. Therefore, in this paper, the bearing fault signature is detected alternatively by estimating and removing nonbearing fault components via a noise cancellation method. In this method, all the components of the stator current that are not related to bearing faults are regarded as noise and are estimated by a Wiener filter. Then, all these noise components are cancelled out by their estimates in a real-time fashion, and a fault indicator is established based on the remaining components which are mainly caused by bearing faults. Machine parameters, bearing dimensions, nameplate values, and the stator current spectrum distribution are not required in the method. The results of online experiments with a 20-hp induction motor under multiple load levels have confirmed the effectiveness of this method.

Detection Method for Open-Circuit Fault in Neutral-Point-Clamped Inverter Systems

Abstract: This paper presents a fault detection method for open-circuit faults of a switching device in neutral-point-clamped inverter systems, which is based on the inherent characteristic of continuous pulsewidth modulation The proposed method is achieved by measuring the pole voltage and its duration time The pole voltage includes information of switching states in the inverter system but not affected by the load Therefore, a fault condition of the inverter system itself can be diagnosed through analysis of pole voltage Compared to conventional fault detection methods, the proposed fault detection method has faster detection capability that is within two sampling times and is much simpler to implement Therefore, the use of the proposed method could minimize harmful effects such as imbalance of dc-link voltage and overstress on other switching devices The validity of the proposed fault detection method is verified through experimental results

Accurate microarchitecture-level fault modeling for studying hardware faults

Abstract: Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault tolerance mechanisms across all levels of the system stack, from the device level to the system level. High-level fault tolerance solutions, such as at the microarchitecture and system levels, are commonly evaluated using statistical fault injections with microarchitecture-level fault models. Since hardware faults actually manifest at a much lower level, it is unclear if such high level fault models are acceptably accurate. On the other hand, lower level models, such as at the gate level, may be more accurate, but their increased simulation times make it hard to track the system-level propagation of faults. Thus, an evaluation of high-level reliability solutions entails the classical tradeoff between speed and accuracy. This paper seeks to quantify and alleviate this tradeoff. We make the following contributions: (1) We introduce SWAT-Sim, a novel fault injection infrastructure that uses hierarchical simulation to study the system-level manifestations of permanent (and transient) gate-level faults. For our experiments, SWAT-Sim incurs a small average performance overhead of under 3x, for the components we simulate, when compared to pure microarchitectural simulations. (2) We study system-level manifestations of faults injected under different microarchitecture-level and gate-level fault models and identify the reasons for the inability of microarchitecture-level faults to model gate-level faults in general. (3) Based on our analysis, we derive two probabilistic microarchitecture-level fault models to mimic gate-level stuck-at and delay faults. Our results show that these models are, in general, inaccurate as they do not capture the complex manifestation of gate-level faults. The inaccuracies in existing models and the lack of more accurate microarchitecture-level models motivate using infrastructures similar to SWAT-Sim to faithfully model the microarchitecture-level effects of gate-level faults.

Decision tree-based fault zone identification and fault classification in flexible AC transmissions-based transmission line

Abstract: Transmission line distance relaying for flexible AC transmission lines (FACTS) including thyristor controlled series compensator (TCSC), STATCOM, SVC and unified power flow controller (UPFC) has been a very challenging task. A new approach for fault zone identification and fault classification for TCSC and UPFC line using decision tree (DT) is presented. One cycle post fault current and voltage samples from the fault inception are used as input vectors against target output ‘1’ for fault after TCSC/UPFC and ‘0’ for fault before TCSC/UPFC for fault zone identification. Similarly, the DT-based classification algorithm takes one cycle data from fault inception of three phase currents along with zero-sequence current and voltage, and constructs the optimal DT for classifying all ten types of shunt faults in the transmission line fault process. The algorithm is tested on simulated fault data with wide variations in operating parameters of the power system network including noisy environment. The results indicate that the proposed method can reliably identify the fault zone and classify faults in the FACTs-based transmission line in large power network.

An architecture for fault detection and isolation based on fuzzy methods

Abstract: Model-based fault detection and isolation (FDI) is an approach with increasing attention in the academic and industrial fields, due to economical and safety related matters. In FDI, the discrepancies between system outputs and model outputs are called residuals, and are used to detect and isolate faults. This paper proposes a model-based architecture for fault detection and isolation based on fuzzy methods. Fuzzy modeling is used to derive nonlinear models for the process running in normal operation and for each fault. When a fault occurs, fault detection is performed using the residuals. Then, the faulty fuzzy models are used to isolate a fault. The FDI architecture proposed in this paper uses a fuzzy decision making approach to isolate faults, which is based on the analysis of the residuals. Fuzzy decision factors are derived to isolate faults. An industrial valve simulator is used to obtain several abrupt and incipient faults, which are some of the possible faults in the real system. The proposed fuzzy FDI architecture was able to detect and isolate the simulated abrupt and incipient faults.

Adaptive Debug and Diagnosis Without Fault Dictionaries

Abstract: Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for `Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.

Determining fault's type and accurate location in distribution systems with DG using MLP Neural networks

Abstract: Finding and designing new methods for determining type and exact location of faults in power system has been a major subject for power system protection engineers in recent years. Fault locating in transmission networks is not very hard and complicated due to low impedance of faults. This job is usually done by distance relays. But, in distribution networks, because of high impedance of fault and its vast variety and also simplicity of protective devices, determining the exact location of faults is very complicated. On the other hand, penetration of distribution generation into distribution networks reinforces the necessity of designing new protection systems for these networks. One of the main capabilities that can improve the efficiency of new protection relays in distribution systems is exact fault locating. In this paper, a new approach for determining the exact fault type and location in distribution systems including distributed generation using MLP neural networks is presented. In the suggested method, after determining the fault type, by normalizing the fault current of the main source, the corresponding trained neural network has been activated and the exact location of occurred fault has been derived. The presented method has been implemented on a sample distribution network, simulated by DIgSILENT Power Factory 13.2, and its performance has been tested. The simulation results show high performance and accuracy of the method and substantiate that it can be used in modern heuristic protection schemes in distribution systems.

Automating the addition of fault tolerance with discrete controller synthesis

Abstract: Discrete controller synthesis (DCS) is a formal approach, based on the same state-space exploration algorithms as model-checking. Its interest lies in the ability to obtain automatically systems satisfying by construction formal properties specified a priori. In this paper, our aim is to demonstrate the feasibility of this approach for fault tolerance. We start with a fault intolerant program, modeled as the synchronous parallel composition of finite labeled transition systems; we specify formally a fault hypothesis; we state some fault tolerance requirements; and we use DCS to obtain automatically a program, having the same behavior as the initial fault intolerant one in the absence of faults, and satisfying the fault tolerance requirements under the fault hypothesis. Our original contribution resides in the demonstration that DCS can be elegantly used to design fault tolerant systems, with guarantees on key properties of the obtained system, such as the fault tolerance level, the satisfaction of quantitative constraints, and so on. We show with numerous examples taken from case studies that our method can address different kinds of failures (crash, value, or Byzantine) affecting different kinds of hardware components (processors, communication links, actuators, or sensors). Besides, we show that our method also offers an optimality criterion very useful to synthesize fault tolerant systems compliant to the constraints of embedded systems, like power consumption.

Insights on Fault Interference for Programs with Multiple Bugs

Abstract: Multiple faults in a program may interact with each other in a variety of ways. A test case that fails due to a fault may not fail when another fault is added, because the second fault may mask the failure-causing effect of the first fault. Multiple faults may also collectively cause failure on a test case that does not fail due to any single fault alone. Many studies try to perform fault localization on multi-fault programs and several of them seek to match a failed test to its causative fault. It is therefore, important to better understand the interference between faults in a multi-fault program, as an improper assumption about test case failure may lead to an incorrect matching of failed test to fault, which may in turn result in poor fault localization. This paper investigates such interference and examines if one form of interference holds more often than another, and uniformly across all conditions. Empirical studies on the Siemens suite suggest that no one form of interference holds unconditionally and that observation of failure masking is a more frequent event than observation of a new test case failure.

A Fault Location Algorithm Based on Circuit Analysis for Untransposed Parallel Transmission Lines

Abstract: This paper proposes a fault-location algorithm for ultra-high-voltage untransposed parallel transmission lines that only use the voltages and currents at the local end. The proposed algorithm uses the voltage equation for the faulted phase of the faulted line. The equation contains the fault distance, fault resistance, and fault current. To obtain the fault current, Kirchhoff's voltage law is applied on the loops of three phases consisting of the faulted line and the adjacent parallel line. The fault current can be represented in terms of the fault distance. Inserting the fault current into the voltage equation results in an equation that contains only two parameters (i.e., the fault distance and fault resistance). The fault distance is estimated by solving the equation. Test results indicated that the algorithm accurately estimates the fault distance regardless of the fault resistance and mutual coupling effects.

Defect-tolerant n 2 -transistor structure for reliable nanoelectronic designs

Abstract: Nanodevices-based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. This study investigates a defect-tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -transistor structure ( N ges2) that guarantees defect tolerance of all N -1 defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4-5 times more transistor defect probability) and at reduced area overhead. For example, the quadded-transistor structure technique requires nearly half the area of the quadded-logic technique.

The Fault Detection Problem

Abstract: One of the most important challenges in distributed computing is ensuring that services are correct and available despite faults. Recently it has been argued that fault detection can be factored out from computation, and that a generic fault detection service can be a useful abstraction for building distributed systems. However, while fault detection has been extensively studied for crash faults, little is known about detecting more general kinds of faults. This paper explores the power and the inherent costs of generic fault detection in a distributed system. We propose a formal framework that allows us to partition the set of all faults that can possibly occur in a distributed computation into several fault classes . Then we formulate the fault detection problem for a given fault class, and we show that this problem can be solved for only two specific fault classes, namely omission faults and commission faults . Finally, we derive tight lower bounds on the cost of solving the problem for these two classes in asynchronous message-passing systems.

Neural network-based approach for early detection of cascading events in electric power systems

Abstract: This study proposes neural modelling and fault diagnosis methods for the early detection of cascading events in electric power systems. A neural-fuzzy network is used to model the dynamics of the power transmission system in fault-free conditions. The output of the neural-fuzzy network is compared to measurements from the power system and the obtained residuals undergo statistical processing according to a fault detection and isolation algorithm. If a fault threshold, defined by the fault detection and isolation (FDI) algorithm, is exceeded then deviation from normal operation can be detected at its early stages and an alarm can be launched. In several cases fault isolation can be also performed, that is the sources of fault in the power transmission system can be also identified. The performance of the proposed methodology is tested through simulation experiments.

Application of Wigner-Ville distribution and probability neural network for scooter engine fault diagnosis

Abstract: An expert system for internal combustion engine fault diagnosis using Wigner-Ville distribution for feature extraction and probability neural network for fault classification is described in this paper. Most of the conventional techniques for fault signal analysis in a mechanical system are based chiefly on the difference of signal amplitude in the time and frequency domains. Unfortunately, in some conditions the performance is limited, such as when analysis signals are non-stationary. In the present study, the Wigner-Ville distribution is proposed for sound emission signal features classification, because it provides high resolution of instantaneous energy density both in time and frequency domains. Meanwhile, the instantaneous power spectrum is presented to obtain high-energy density when the engine fault condition occurs. These features of signals are classified using the probability neural network. To examine the efficiency of the probability neural network, both back-propagation and radial basis function neural networks are used in comparison with fault classification. The experimental results showed all three networks can achieve high recognition rate with feature extraction using Wigner-Ville distribution method. It also suggested the probability neural network can complete training in an extremely short time.

Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA

Abstract: This paper presents a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). The proposed FPGA BIST structure can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs. The applications on XC4000-series FPGAs show that 100% fault coverage of the proposed FPGA BIST structure can be obtained. Additionally, the test results reveal that good performance in fault detection and fault diagnosis on both interconnect resources and CLBs can be achieved at levels similar to those required in previous works.

A new method for fault detection during power swing in distance protection

Abstract: During a power swing, currents and voltages behave such as a fault. Therefore, Power swing blocking function in distance relays is necessary to discriminate between a power swing and a fault. Otherwise power swings can be considered as a fault and causes relay trip. The main problem happens when during power sings a fault occurs. In this case, distance relays should be unblocked. In this paper, a new method based on the DC component of fault currents will be proposed to detect a fault during power swing blocking. The proposed method can detect single-phase to ground, two-phase to ground and three-phase fault. Applying the new method on a sample network reveals the features of the method.

Call-stack pattern matching for problem resolution within software

Abstract: A method of diagnosing a fault condition within software can include, responsive to a fault condition within a computing system belonging to an organization, automatically sending call-stack information for the fault condition to a first server within the organization. Within the first server, the call-stack information for the fault condition can be compared with call-stack information from prior fault conditions that occurred within the organization to determine whether the call-stack information for the fault condition matches call-stack information from one of the prior fault conditions. The method further can include sending the call-stack information to a second server for comparison with call-stack information from prior fault conditions that occurred within at least one different organization if the call-stack information for the fault condition does not match.

Double circuit transmission line Fault Distance Location using Artificial Neural Network

Abstract: Distance relays used for protection of transmission lines have problems of under-reach, over-reach and maloperation due to high impedance faults. Further the problem is compounded when the distance relays are used for protection of double circuit transmission lines due to effect of zero sequence mutual coupling. Different types of faults on a protected transmission line should be located correctly. This paper presents a single neural network for fault distance location for all the ten types of faults (3 LG, 3 LLG, 3 LL, 1 LLL) in both the circuits of a double circuit transmission line fed from sources at both the end. This technique uses only one end data and accurate fault distance location is achieved after one cycle from the inception of fault. The proposed Artificial Neural Network (ANN) based Fault Distance Locator uses fundamental components of three phase current signals of both the circuits & three phase voltage signals to learn the hidden relationship in the input patterns. An improved performance is obtained once the neural network is trained suitably, thus performing correctly when faced with different system parameters and conditions i.e. varying fault type, fault location, fault resistance, fault inception angle, presence of mutual coupling and remote source infeed.

Fault Detection and Isolation for Deep Space Satellites

Abstract: A method for detecting faults in the navigation and control system of deep space satellites is presented. A new method for computing the probability of a fault given multiple different types of residuals processors is presented. The method uses the Shiryayev sequential probability ratio test to estimate the probability of the presence of a fault signal given the residuals generated from either parity relationships or fault detection filters, a fault map of the impact of each fault signal on the residuals, and an adaptive fault estimation scheme that enables processing with fewer residuals. This new methodology is applied to the detection of the fault signals in the attitude control system and navigation system of deep space satellites. First a sensor fusion process is presented for blending star tracker data, gyro data, accelerometer data, and information from the vehicle control system to form the best estimate of the navigation state. Then a set of fault detection filters are developed that detect and uniquely identify faults in each of the sensors or actuators. Decision-making is handled through the sequential processing. Simulation results for a single-satellite system are presented.

Multi-sensor fault recovery in the presence of known and unknown fault types

Abstract: This paper proposes an efficient online, hybrid, Bayesian multi-sensor fusion algorithm for target tracking in the presence of modelled and unmodelled faults. The algorithm comprises two stages. The first stage attempts to remove modelled faults from each individual sensor estimate. The second stage de-emphasises estimates which have been subject to unanticipated faults and are still faulty despite undergoing the Stage 1 fault recovery process. The algorithm is a computationally efficient and decentralisable hybrid of two standard approaches to fault detection, namely model-based fault detection and majority voting. The algorithm is tested on two distinct simulated scenarios (1) when the target process model does not match reality and (2) in the presence of simultaneous modelled and unanticipated faults.