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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, an adaptive Kalman filtering scheme is presented for estimation of the 60 Hz phasor quantities, fault type identification, distance protection, and fault location, where the current and voltage data of each phase are simultaneously processed in two Kalman filter models.
Abstract: An adaptive Kalman filtering scheme is presented for estimation of the 60 Hz phasor quantities, fault type identification, distance protection, and fault location. The current and voltage data of each phase are simultaneously processed in two Kalman filter models. One model assumes that the phase is unfaulted, while the other model assumes the features of a faulted phase. The condition of the phase is then decided from the computed a posteriori probabilities. Upon the secure identification of the condition of the phase, the corresponding Kalman filtering model continues to obtain the best estimates of the current or voltage state variables. Upon convergence to highly accurate values, the appropriate current and voltage pairs are selected to decide the zone of the fault and the fault location. The scheme was tested on digitally simulated data. The fault classification was doubly secure using both voltage and current data. The convergence of estimates reached exact values within half a cycle. >

69 citations

Journal ArticleDOI
TL;DR: In this article, a fault location algorithm which does not need to classify the fault type before location estimation is presented, which can locate all types of shunt faults including the cross-country and evolving faults.

69 citations

Journal ArticleDOI
01 Oct 2009
TL;DR: The demonstration that DCS can be elegantly used to design fault tolerant systems, with guarantees on key properties of the obtained system, such as the fault tolerance level, the satisfaction of quantitative constraints, and so on is demonstrated.
Abstract: Discrete controller synthesis (DCS) is a formal approach, based on the same state-space exploration algorithms as model-checking. Its interest lies in the ability to obtain automatically systems satisfying by construction formal properties specified a priori. In this paper, our aim is to demonstrate the feasibility of this approach for fault tolerance. We start with a fault intolerant program, modeled as the synchronous parallel composition of finite labeled transition systems; we specify formally a fault hypothesis; we state some fault tolerance requirements; and we use DCS to obtain automatically a program, having the same behavior as the initial fault intolerant one in the absence of faults, and satisfying the fault tolerance requirements under the fault hypothesis. Our original contribution resides in the demonstration that DCS can be elegantly used to design fault tolerant systems, with guarantees on key properties of the obtained system, such as the fault tolerance level, the satisfaction of quantitative constraints, and so on. We show with numerous examples taken from case studies that our method can address different kinds of failures (crash, value, or Byzantine) affecting different kinds of hardware components (processors, communication links, actuators, or sensors). Besides, we show that our method also offers an optimality criterion very useful to synthesize fault tolerant systems compliant to the constraints of embedded systems, like power consumption.

69 citations

Proceedings ArticleDOI
30 Sep 2001
TL;DR: In this article, the authors developed the foundations of a technique for detection and categorization of dynamic/static eccentricities and bar/end-ring connector breakages in squirrel-cage induction motors.
Abstract: This paper develops the foundations of a technique for detection and categorization of dynamic/static eccentricities and bar/end-ring connector breakages in squirrel-cage induction motors that is not based on the traditional Fourier transform frequency-domain spectral analysis concepts. Hence, this approach can distinguish between the "fault signatures" of each of the following faults: eccentricities, broken bars, and broken end-ring connectors in such induction motors. Furthermore, the techniques presented here can extensively and economically predict and characterize faults from the induction machine adjustable-speed drive design data without the need to have had actual fault data from field experience. This is done through the development of dual-track studies of fault simulations and, hence, simulated fault signature data. These studies are performed using our proven time-stepping coupled finite-element-state-space method to generate fault case performance data, which contain phase current waveforms and time-domain torque profiles. Then, from this data, the fault cases are classified by their inherent characteristics, so-called "signatures" or "fingerprints." These fault signatures are extracted or "mined" here from the fault case data using our novel time-series data mining technique. The dual track of generating fault data and mining fault signatures was tested here on dynamic and static eccentricities of 10% and 30% of air-gap height as well as cases of one, three, six, and nine broken bars and three, six, and nine broken end-ring connectors. These cases were studied for proof of principle in a 208 V 60 Hz four-pole 1.2 hp squirrel-cage three-phase induction motor. The paper presents faulty and healthy performance characteristics and their corresponding so-called phase space diagnoses that show distinct fault signatures of each of the above-mentioned motor faults.

69 citations

Journal ArticleDOI
TL;DR: This work presents a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay faultmodel (PDFM) by starting from a function description as a binary decision diagram and generated by a linear time mapping algorithm.
Abstract: We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.

68 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846