Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Robust fault isolation for a class of non-linear input?output systems

Abstract: The design and analysis of fault diagnosis methodologies for non-linear systems has received significant attention recently. This paper presents a robust fault isolation scheme for a class of non-linear systems with unstructured modelling uncertainty and partial state measurement. The proposed fault diagnosis architecture consists of a fault detection and approximation estimator and a bank of isolation estimators. Each isolation estimator corresponds to a particular type of fault in the fault class. A fault isolation decision scheme is presented with guaranteed performance. If at least one component of the output estimation error of a particular fault isolation estimator exceeds the corresponding adaptive threshold at some finite time, then the occurrence of that type of fault can be excluded. Fault isolation is achieved if this is valid for all but one isolation estimator. Based on the class of non-linear systems under consideration, fault isolability conditions are rigorously investigated, characterizin...

Test generation for large logic networks

Abstract: A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.

Integration of non-classical faults in standard March tests

Abstract: New fault models like the unrestored write and the false write through faults and suitable test algorithms have recently been developed by several authors. These tests are applied in addition to March tests. Since a March test algorithm can be implemented in many different ways and still be effective in detecting its target faults, we have what we call degrees of freedom in the test space. In this paper it is shown, that for commonly used memory organizations tests for the unrestored write and false write through faults can be integrated in March test sequences. It is shown how to design address sequence generators and address dependent data for March tests, that generate all the patterns required for the detection of those faults. The detection properties of the original March tests are retained. The additional overhead in terms of silicon area and timing for an on-chip realization of a built-in March self-test with the added fault detection features is negligible and the test application time remains unchanged.

Dependability analysis using a fault injection tool based on synthesizability of HDL models

Abstract: This paper presents a fault injection tool called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: (1) an arithmetic processor with a non-synthesizable Verilog model, called ARP; and (2) a VHDL model of 32-bit processor with a synthesizable ALU, called DP32. The results show that depending on the fault injection points in the ARP, the effects of faults were significantly different, while in the case of DP32, the fault coverage varied between 51 to 56 percent of total faults injected.

An experimental approach to analog fault models

Abstract: A comprehensive approach to model faults in analog circuits and systems based on experimental statistics of manufacturing defects is presented. A case study based on a simple sample-and-hold circuit is discussed with specific results. It is shown that the digital fault models are applicable to analog and mixed-signal circuits but they account only for catastrophic faults. Out-of-specification faults occur as often as catastrophic faults and must be addressed in any DFT (discrete Fourier transform) technique or test generation algorithm. >