Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die

Abstract: This paper presents experimental results from circuits specially implemented to evaluate a new technique for detecting delay faults in scan based designs. The faults are detected by observing circuit outputs at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. For this study a simple datapath circuit was designed and fabricated through MOSIS. Extra capacitive delays were deliberately introduced in a copy of the design. The test results presented here clearly establish the signGCant potential of the proposed new delay testing approach.

Properties of the input pattern fault model

Abstract: Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Transient fault detection system and method using Hidden Markov Models

Abstract: A transient fault detection system and method is provided that facilitates improved fault detection performance in transient conditions. The transient fault detection system provides the ability to detect symptoms of engine faults that occur in transient conditions. The transient fault detection system includes a Hidden Markov Model detector that receives sensor data during transient conditions and determines if a fault has occurred during the transient conditions. Detected faults can then be passed to a diagnostic, system where they can be passed as appropriate to maintenance personnel.

Fault model and performance evaluation of an inverter-fed permanent magnet synchronous motor under winding shorted turn and inverter switch open

Abstract: To analyse influences under various fault conditions, a fault model of an inverter-fed permanent magnet (PM) synchronous motor drive that can be used for a performance assessment of a diagnostic algorithm is presented. For fault conditions of a drive system, a short-circuited turn in the stator winding, switching device open in pulse width modulated inverter and the isolation between the inverter and motor are considered. Even though the conventional dq model is widely used to control an AC motor, it cannot be used directly for the analysis of a motor fault, since three-phase balanced condition does not hold under such conditions, and thus, it is not easy to obtain phase voltage inputs of motor from the pole voltage. To overcome this limitation, a fault model of an inverter-fed PM synchronous motor is derived using the line voltage, which can be effectively used to evaluate the performance of a fault detection algorithm. A test motor producing short-circuited turn in the stator winding is built. The validity of the proposed fault model is verified through the comparative simulations and experiments using digital signal processor TMS320F28335 under various fault conditions.

Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring

Abstract: A new method for the testing and fault detection of analog integrated circuits is presented. Time-domain testing followed by spectral analysis of the power-supply current is used to detect both DC and AC faults. Spectral analysis is applied since the tolerances on the circuit parameters make a direct comparison of waveforms impossible. For the fault detection a probabilistic decision rule is proposed based on a multivariate statistical analysis. Since no extra testing pin is needed and the on-line calculation effort is small, the method can be used for wafer-probe testing as well as final production testing. In addition, a methodology for the selection of the input stimulus is presented that improves the test-ability. Examples demonstrate the efficiency and the effectiveness of the algorithms.