Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Harmonic Order Tracking Analysis: A Novel Method for Fault Diagnosis in Induction Machines

Abstract: The diagnosis of induction machines using Fourier transform relies on tracking the frequency signature of each type of fault in the current's spectrum, but this signature depends on the machine's slip and the supply frequency, so it must be recomputed for each working condition by trained personnel or by diagnostic software. Besides, sampling the current at high rates during long times is needed to achieve a good spectral resolution, which requires large memory space to store and process the current spectra. In this paper, a novel approach is proposed to solve both problems. It is based on the fact that each type of fault generates a series of harmonics in the current's spectrum, whose frequencies are multiples of a characteristic main fault frequency. The tracking analysis of the fault components using the harmonic order (defined as the frequency in per unit of the main fault frequency) as independent variable instead of the frequency generates a unique fault signature, which is the same for any working condition. Besides, this signature can be concentrated in just a very small set of values, the amplitudes of the components with integer harmonic order. This new approach is introduced theoretically and validated experimentally.

Delay testing of digital circuits by output waveform analysis

Abstract: A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.

Principles of fault tolerance

Abstract: The demand for continuously available electronic systems increases every day. Transaction processing, communications systems, and critical processes all require nonstop, fault tolerant operation. Creating a fault tolerant or highly available system can be achieved by following four basic principles: redundancy, fault isolation, fault detection and annunciation, and on-line repair. This paper is a tutorial that presents those four principles after reviewing some fundamentals of reliability and availability. It concludes with an expanded discussion on implementing redundancy. Special considerations for high availability and fault tolerance in distributed power systems are highlighted.

A Fault-Location Algorithm for Series-Compensated Double-Circuit Transmission Lines Using the Distributed Parameter Line Model

Abstract: A new fault-location algorithm for series-compensated double-circuit transmission lines utilizing two-terminal unsynchronized voltage and current measurements is presented in this paper. The mutual coupling between the parallel lines in the zero-sequence network is fully considered. The distributed parameter line model is adopted to fully take into account the shunt capacitance of the line. By formulating voltages and currents at the fault point in terms of the unknown fault location, boundary conditions under different fault types are used to derive the fault location. Two subroutines assuming the fault occurs on the left or right side of the series compensator are developed and the principle to identify the correct fault-location estimate is described. Matlab SimPowerSystems is employed to generate cases under diverse fault conditions for validating the proposed fault-ocation algorithm. Evaluation studies have shown that the proposed algorithm has achieved quite accurate results.

Truth-Table Verification of an Iterative Logic Array

Abstract: This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.