Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
Papers published on a yearly basis
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20 Jan 1995TL;DR: In this article, a fault current sensor device is used to detect and distinguish abnormal current events such as momentary outage, sustained outage, normal overload, and inrush on an alternating current overhead or underground power transmission or distribution line.
Abstract: A fault current sensor device (1) which can detect and distinguish abnormal current events such as momentary outage, sustained outage, normal overload, and inrush on an alternating current overhead or underground power transmission or distribution line (2). The sensing device (1) is attached to the power line (2) and, when a fault condition is detected, a Schmitt trigger (15) wakes up a microprocessor (11) from a sleep mode. The microprocessor distinguishes which one of the fault current conditions has occurred on the power line (2), and a transceiver (3) transmits an alarm signal to a designated ground station. The device (1) can be remotely programmed to alter its trigger or threshold level or time delay to reset the device (1) when a fault has occurred. When normal current levels return, the device can be reset by itself or remotely from the ground station. The fault sensor device is powered by capacitors (8) which are charged by photovoltaic cells (7) or a current transformer (18).
64 citations
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TL;DR: In this article, a novel use of artificial neural network (ANN) for fault detection and fault location in a low voltage DC bus microgrid system is presented, which can be fast detected and then isolated without de-energizing the entire system, hence achieving a more reliable DC microgrid.
64 citations
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03 Apr 1987
TL;DR: In this article, a multiple-redundant computer system with multiple voter circuits and multiple fault detection logic is presented, where the fault status words generated by the fault detector are also subject to a voted read by the multiple computational devices.
Abstract: A multiple-redundant computer system having multiple computational devices (40a, 40b, 40c) operating in synchronism, multiple voter circuits (30a, 30b, 30c) to provide voted memory reading operations for the devices, and multiple fault detection logic (44a, 44b, 44c) for the detection of failures of the computational devices. Fault status words generated by the fault detection logic are also subject to a voted read by the multiple computational devices, thereby permitting detection of errors in the fault detection logic itself, as well as in the computational devices. The module structure of the invention also permits removal and replacement of circuit modules, each including a computational device and fault detection logic, without disconnecting power from the entire system.
63 citations
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08 Sep 1993
TL;DR: In this article, a fault location estimation method is proposed to estimate the fault location regardless of the fault resistance, load current, mutual coupling effects from a parallel line, uncertainties in zero sequence values, shunt elements, and X/R characteristic of the system.
Abstract: A fault location system comprises voltage/current transducers 10A, 10B located at terminals A and B, respectively; digital relays 12A and 12B respectively coupled to transducer blocks 10A and 10B; and a fault location estimation processor 14, which may comprise a substation controller at substation S A or substation S B , a relay at A or B, a stand alone computer at A or B, or a computer at a central location. The digital relays receive analog voltage and current signals (V A , I A , V B , I B ) from the respective transducers and output digital phasor or oscillographic data to the fault location estimation block. The fault location estimation block is programmed to provide the fault location parameter m. The fault location estimation provided by the inventive technique is unaffected by the fault resistance, load current, mutual coupling effects from a parallel line, uncertainties in zero sequence values, shunt elements, and X/R characteristic of the system. The fault location can be estimated accurately even in cases of substantial resistance and load flow. In addition, the invention does not require synchronization of the data received from the respective A and B terminals, nor does it require pre-fault data or fault type selection.
63 citations
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06 Mar 1995TL;DR: A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults consisting of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixed-signal circuit layout.
Abstract: A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults. It comprises of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixed-signal circuit layout and the automatic analogue fault simulation program AnaFAULT which can handle arbitrary catastrophic and parametric faults. For a fabricated integrated VCO circuit the capabilities of the tool are demonstrated and simulation results are presented. >
63 citations