Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Generating test cases for EFSM with given fault models

Abstract: A test case generation method is proposed for the conformance testing of communication protocols. Given a protocol specification and a fault model, both specified by extended finite state machines (EFSMs), the proposed method generates test cases that detect the given faults. A theoretical model is proposed to describe the dynamic properties of EFSMs. Test cases can be generated by analyzing the differences in the dynamic properties between the specification and the fault models. >

A Novel Fault-Location Algorithm for Double-Circuit Transmission Lines Without Utilizing Line Parameters

Abstract: This paper puts forward a novel algorithm for locating faults on double-circuit transmission lines using two-end unsynchronized current measurements. The algorithm does not require line parameters, which is a radical step forward compared to existing approaches, which require this information, so it can be considered as a settings-free algorithm. Only the positive-sequence current phasors during the fault are processed for determining the sought distance to fault and the synchronization angle, limiting thus the amount of data needed to be transferred from each line terminal. The proposed algorithm is derived by applying the Kirchhoff's voltage law around the parallel circuits loops during the fault. The algorithm is applicable for both transposed and untransposed double-circuit lines and is independent of the fault type. Evaluation studies using reliable Alternative Transients Program-Electromagnetic Transients Program simulation data verify that the accuracy of the proposed algorithm is very high under various fault resistances, fault locations, and source impedances.

Programmable logic array

Abstract: Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaluated sequentially. A multiple input signature register which uses XQ + 1 as its characteristics polynomial is used to evaluate the test results, where Q is the number of outputs. The final signature can be further compressed into only ONE bit. Instead of only determining the probability of fault detection, in this scheme, the fault detection capability has been analyzed using both the stuck at fault and the contact fault model. It can be shown that all of these faults can be detected. Shorts between two adjacent lines can be detected by using NOR gates.

A Fault Location Algorithm Based on Circuit Analysis for Untransposed Parallel Transmission Lines

Abstract: This paper proposes a fault-location algorithm for ultra-high-voltage untransposed parallel transmission lines that only use the voltages and currents at the local end. The proposed algorithm uses the voltage equation for the faulted phase of the faulted line. The equation contains the fault distance, fault resistance, and fault current. To obtain the fault current, Kirchhoff's voltage law is applied on the loops of three phases consisting of the faulted line and the adjacent parallel line. The fault current can be represented in terms of the fault distance. Inserting the fault current into the voltage equation results in an equation that contains only two parameters (i.e., the fault distance and fault resistance). The fault distance is estimated by solving the equation. Test results indicated that the algorithm accurately estimates the fault distance regardless of the fault resistance and mutual coupling effects.