Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
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TL;DR: In this paper, a decision support system (DSS) using circuit breaker information for online fault section estimation in power systems is presented, which automatically creates rules for knowledge representation and develops an efficient diagnosis procedure.
Abstract: This paper presents a novel decision support system (DSS) using circuit breaker information for online fault section estimation in power systems. The new representation of knowledge and approach to resolving fault diagnosis problems are included in the proposed system. The DSS automatically creates rules for knowledge representation and develops an efficient diagnosis procedure. After the fault section is estimated, the logical reasoning approach uses the relay information to further validate the candidate fault section and circuit breaker status. Test results verify that the DSS can obtain rapid and accurate diagnosis results with flexibility and portability for fault diagnosis of diverse power systems. Those results further demonstrate the feasibility of applying the proposed DSS to actual power system fault section estimation.
60 citations
TL;DR: In this article, a novel time-delay switched descriptor state observer is proposed to estimate both the state and sensor fault, and an efficient fault-tolerant operation can be realised via sensor fault compensation.
Abstract: In this article, the problems of sensor fault estimation and compensation approaches for time-delay switched systems are investigated based on a switched descriptor observer approach. First, a novel time-delay switched descriptor state observer is proposed to estimate both the state and sensor fault. The proposed observer technique is also extended to systems with nonlinearities. Then, based on the estimation of the sensor fault, an efficient fault-tolerant operation can be realised via sensor fault compensation. Finally, an example is given to show the efficiency of the developed techniques.
59 citations
TL;DR: To release the limitations of a fully connected network and a single faulty type, the problem is reconsidered in a general network and the proposed protocol uses the minimum number of message exchanges and can tolerate the maximum number of allowable faulty components to make each fault-free processor reach an agreement.
Abstract: In early stage, the Byzantine agreement (BA) problem was studied with single faults on processors in either a fully connected network or a nonfully connected network. Subsequently, the single fault assumption was extended to mixed faults (also referred to as hybrid fault model) on processors. For the case of both processor and link failures, the problem has been examined in a fully connected network with a single faulty type, namely an arbitrary fault. To release the limitations of a fully connected network and a single faulty type, the problem is reconsidered in a general network. The processors and links in such a network can both be subjected to different types of fault simultaneously. The proposed protocol uses the minimum number of message exchanges and can tolerate the maximum number of allowable faulty components to make each fault-free processor reach an agreement.
59 citations
01 Jan 1993
TL;DR: Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing is presented.
Abstract: Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuckopen-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing.
59 citations
29 Aug 1989
TL;DR: The authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle and present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits.
Abstract: The authors address the issues involved in providing an integrated test generation/fault simulation environment on a parallel processor. They propose heuristics to partition faults for parallel test generation with minimization of the overall run time and test length as an objective. For efficient utilization of available processors, the work load has to be balanced at all times. Since it is very difficult to predict a priori how difficult it is to generate a test for a particular fault, the authors propose a load-balancing method which uses static partitioning initially and then dynamic allocation of work for processors which become idle. They present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits. The main contribution of the work described is to show that if one is not careful in the design of a parallel algorithm, apart from inefficient utilization of available processors, degradation in the quality of solutions can occur. >
59 citations