Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Universal fault simulation using fault tuples

Abstract: We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.

CMOS bridges and resistive transistor faults: IDDQ versus delay effects

Abstract: Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing. >

Analysis and methodology for multiple-fault diagnosis

Abstract: In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Abstract: This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

Automatic test generation for model-based real-time fault diagnostic systems

Abstract: In a real-time diagnostic system, an alarm sequence generator is used to test the correctness of a fault model. The fault model describes an industrial process being monitored. The alarm sequence generator reads the fault model and generates a user interface, from which specific components can be selected for failure at specified times. The alarm sequence generator assembles all alarms that are causally downstream from the selected set of faulty components and determines which alarms should be turned on based on probabilistic and temporal information in the fault model. The timed alarm sequence can be used by an expert to measure the correctness of a particular model, or can be used as input into a diagnostic system to measure the correctness of the diagnostic system.