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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


Papers
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Journal ArticleDOI
TL;DR: A modular yet integrated approach to the problem of fast fault detection and classification that can be model-based or model-free, and which would be applicable to arbitrary dynamic systems.
Abstract: This paper presents a modular yet integrated approach to the problem of fast fault detection and classification. Although the specific application example studied here is a power system, the method would be applicable to arbitrary dynamic systems. The approach is quite flexible in the sense that it can be model-based or model-free. In the model-free case, we emphasize the use of concepts from signal processing and wavelet theory to create fast and sensitive fault indicators. If a model is available then conventionally generated residuals can serve as fault indicators. The indicators can then be analyzed by standard statistical hypothesis testing or by artificial neural networks to create intelligent decision rules. After a detection, the fault indicator is processed by a Kohonen network to classify the fault. The approach described here is expected to be of wide applicability. Results of computer experiments with simulated faulty transmission lines are included.

57 citations

Patent
29 Jun 2000
TL;DR: In this article, a shadow mode created by a fault handling virtual machine is invoked to bring the computer system back to a normal operating state in which the component or action causing the initial nonrecoverable fault is avoided.
Abstract: Methods, apparatus, and computer program products are disclosed for analyzing and recovering from severe to catastrophic faults in a computer system. When a fault that cannot be handled by the computer system's normal fault handling processes, a shadow mode created by a fault handling virtual machine is invoked. The fault handling virtual machine executes only when the normally nonrecoverable fault is encountered and executes as a triangulated or shadow mode on the system. Once shadow mode is invoked, fault context data is collected on the system and used to analyze and recover from the fault. More specifically, one or more post-fault stable states are constructed by the fault handling virtual machine. These stable states are used to bring the computer system back to a normal operating state in which the component or action causing the initial nonrecoverable fault is avoided. Persistent faults may be encountered while the virtual machine is attempting to recover from the initial fault.

56 citations

Patent
09 Dec 1986
TL;DR: In this paper, a method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards is presented.
Abstract: A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.

56 citations

Proceedings ArticleDOI
01 Jan 1995
TL;DR: A diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient and faster than an earlier work based on distinguishability matrices and is faster and more memory efficient than a recent method based on lists of indistinguishable faults.
Abstract: This paper describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices and is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits.

56 citations

Patent
24 Jul 2003
TL;DR: In this paper, a system and method that provides improved fault detection in turbine engines is disclosed, which provides the ability to detect symptoms of engine faults based on a relatively limited number of engine parameters that are sampled relatively infrequently.
Abstract: A system and method that provides improved fault detection in turbine engines is disclosed. The fault detection system provides the ability to detect symptoms of engine faults based on a relatively limited number of engine parameters that are sampled relatively infrequently. The fault detection system includes a sensor data processor that receives engine sensor data during operation and augments the sensor data. The augmented data set is passed to a fuzzy logic inference system that determines the likelihood that a fault has occurred. The inference system output can then be passed to a diagnostic system where evaluation of the output may yield a detailed diagnostic result and a prediction horizon.

56 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846