Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
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TL;DR: In this paper, the authors proposed a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis, which gives rms profiles of the fault currents of interest (IIDG contributions and the fault current the protective device will see).
Abstract: This paper shows that the current an inverter interfaced distributed generator (IIDG) contributes to a fault varies considerably, due mainly to fast response of its controller. This paper proposes a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis. The proposed method gives rms profiles of the fault currents of interest (IIDG contribution and the fault currents the protective device will see). Test results, based on a prototype feeder, show that the proposed approach can estimate the fault current's contributions under both balanced and unbalanced fault conditions.
240 citations
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01 Nov 1990TL;DR: In this article, the authors describe a very accurate fault location technique which uses post-fault voltage and current derived at both line ends, independent of fault resistance and the method does not require any knowledge of source impedance.
Abstract: The authors describe a very accurate fault location technique which uses post-fault voltage and current derived at both line ends. Fault location is independent of fault resistance and the method does not require any knowledge of source impedance. It maintains high accuracy for untransposed lines and no fault type identification is required. The authors present the theory of the technique and the results of simulation studies to determine its performance.<
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239 citations
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26 Oct 1991TL;DR: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed and can be added to existing test pattern generators without compromising fault coverage.
Abstract: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >
237 citations
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TL;DR: In this paper, a simple and low-cost open-circuit fault detection and identification method for a PWM voltage-source inverter employing a permanent magnet synchronous motor is proposed.
Abstract: In this paper, a simple and low-cost open-circuit fault detection and identification method for a pulse-width modulated (PWM) voltage-source inverter (VSI) employing a permanent magnet synchronous motor is proposed. An open-circuit fault of a power switch in the PWM VSI changes the corresponding terminal voltage and introduces the voltage distortions to each phase voltage. The proposed open-circuit fault diagnosis method employs the model reference adaptive system techniques and requires no additional sensors or electrical devices to detect the fault condition and identify the faulty switch. The proposed method has the features of fast diagnosis time, simple structure, and being easily inserted to the existing control algorithms as a subroutine without major modifications. The simulations and experiments are carried out and the results show the effectiveness of the proposed method.
229 citations
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TL;DR: In this article, a methodology for diagnostics of fixture failures in multistage manufacturing processes (MMP) is presented, which is based on the state-space model of the MMP process, which includes part fixturing layout geometry and sensor location.
Abstract: This paper presents a methodology for diagnostics of fixture failures in multistage manufacturing processes (MMP). The diagnostic methodology is based on the state-space model of the MMP process, which includes part fixturing layout geometry and sensor location. The state space model of the MMP characterizes the propagation of fixture fault variation along the production stream, and is used to generate a set of predetermined fault variation patterns. Fixture faults are then isolated by using mapping procedure that combines the Principal Component Analysis (PCA) with pattern recognition approach. The fault diagnosability conditions for three levels: (a) within single station, (b) between stations, and (c) for the overall process, are developed. The presented analysis integrates the state space model of the process and matrix perturbation theory to estimate the upper bound for isolationability of fault pattern vectors caused by correlated and uncorrelated noises. A case study illustrates the proposed method.
228 citations