Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

Advanced techniques for GA-based sequential ATPGs

Abstract: Genetic Algorithms (GAs) have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of the GA-based ATPG algorithm proposed by Prinetto et al. (1994): in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved fault coverage and required CPU time.

Robust Variable Structure Controller Design for Fault Tolerant Flight Control

Abstract: In this paper, a variable structure control (VSC) based model following control system that possesses fault detection and isolation(FDI) capability as well as fault tolerance property is proposed. With the scheme, parameter estimation process for reconfigurable control is not necessary. The main idea of the proposed algorithm stems from the fact that nonlinear control of VSC counteracts to external disturbances. The proposed algorithm is shown to be very useful for the case of control effector damage in aircraft, where the parameter change and external fault signal satisfy the matching conditions. With the comparison of nonlinear control suppressing fault effect and adequate outputs, it is also possible to determine how serious the damage is. The numerical result shows the applicability of the proposed algorithm in this paper.

Simulating Resistive-Bridging and Stuck-At Faults

Abstract: The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time

High-speed superimposed-based protection of series-compensated transmission lines

Abstract: This study presents a sub-cycle power frequency-based fault direction discrimination and fault classification algorithm for the series-compensated transmission lines. Also, it provides an accurate estimation for the fault occurrence instant which is helpful in synchronised waveforms-based pilot protective schemes. The proposed algorithm is based on capturing the initial change in the voltage and current waveforms caused by occurrence of a fault. The high-frequency components of the fault signals are first filtered out, and then the signals are sampled at a relatively low sampling rate. Unlike the conventional relative-phase-angle-based directional relays, the proposed algorithm is not affected by the current and voltage inversion phenomena due to the presence of series capacitor in the fault loop. Extensive simulation studies are performed to evaluate the proposed algorithm performance. The obtained results show that the proposed algorithm provides a simple and a very fast and reliable protection technique for power transmission lines. This algorithm also covers non-compensated transmission lines and is able to well discriminate the fault direction even if the post-fault voltage amplitude becomes too small. It is also tested using some real data recorded from a high-voltage transmission system.

Calculation of Internal Fault Currents in Synchronous Machines

Abstract: An internal fault in the armature winding of a synchronous machine occurs at the breakdown of either the minor insulation (turn-to-turn fault) or the major insulation (phase-to-ground fault). The faulty synchronous machine is represented by an equivalent circuit in three symmetrical components which can be connected to the corresponding network. The fault currents can be calculated from the obtained equivalent network. The calculation of internal fault currents has been programmed for the IBM 7090 digital computer, and the calculated values have been compared with the experimental results.