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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


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Journal ArticleDOI
TL;DR: An efficient fault simulation procedure for this model is described and an efficient test generation procedure is discussed that combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.
Abstract: We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.

46 citations

Journal ArticleDOI
TL;DR: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented, in which a given path is tested by augmenting the netlist model of the circuit with a logic block.
Abstract: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing. >

46 citations

Journal ArticleDOI
TL;DR: In this paper, a hierarchical diagnosis model based on fault tree analysis (FTA) and two other diagnosis models, respectively, based on the logic and sequential control of manufacturing systems which are usually controlled by a programmable logical controller (PLC).

46 citations

Journal ArticleDOI
TL;DR: In this article, an online basis fault-detecting scheme for synchronous motor operation is presented, which is achieved by monitoring the second-order harmonic component in q-axis current and the fault is detected by comparing these components with those in normal conditions.
Abstract: To detect faults in an inverter-fed permanent magnet synchronous motor drive under the circumstance having faults in a stator winding and inverter switch, an online basis fault-detecting scheme during motor operation is presented. The proposed scheme is achieved by monitoring the second-order harmonic component in q-axis current and the fault is detected by comparing these components with those in normal conditions. The non-fault harmonic data in an arbitrary operating condition are determined using the linear interpolation method with several sample harmonic data pre-measured in the stage of the initial drive setup. Once the fault is detected, the operating mode is changed to identify a fault source using the phase current waveform. To verify the effectiveness of the proposed fault detecting scheme, a test motor to allow inter-turn short in the stator winding has been built. The entire control system including harmonic analysis and fault detecting algorithm is implemented using digital signal processor TMS320F28335. Without requiring an additional hardware, the fault can be effectively detected by the proposed scheme during operation so long as the steady-state condition is satisfied.

46 citations

Journal ArticleDOI
01 Mar 1999
TL;DR: In this paper, an accurate fault location algorithm for a single phase-to-earth fault on a two-parallel transmission line is presented, in which the source impedance of the remote end is not involved.
Abstract: An accurate algorithm for fault location of a single phase-to-earth fault on a two-parallel transmission line is presented. The faulted phase circuit and the zero-sequence circuit of the two-parallel line are used as a fault location model, in which the source impedance of the remote end is not involved. The algorithm effectively eliminates the effect of load flow and fault resistance on the accuracy of fault location. It embodies an accurate fault location by measuring only local data and is used in a procedure that provides the automatic determination of faulted types and phases, rather than requiring an engineer to specify them. Simulation results have demonstrated the validity of the algorithm under the condition of a phase-to-earth fault.

46 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846