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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


Papers
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Proceedings ArticleDOI
01 Jun 1991
TL;DR: The single transition fault model is augmented by carefully selected multiple transition faults which potentially increase the coverage of single stuck-at faults and experimental results for stuck- at faults are presented.
Abstract: A complete method is presented for generating tests for sequential machines. The transition fault model is employed, and the machine is assumed to be described by a state table. The test generation algorithm described is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given transition fault, the algorithm provides either a test, or a proof that the fault is undetectable. The relationship between transition faults and stuck-at faults is investigated. The single transition fault model is augmented by carefully selected multiple transition faults which potentially increase the coverage of single stuck-at faults. A method to achieve 100% fault efficiency for stuck-at faults is then proposed, and experimental results for stuck-at faults are presented.

45 citations

Proceedings ArticleDOI
05 Jan 1994
TL;DR: A novel fault independent algorithm for redundancy identification in combinational circuits based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is undetectable and hence redundant is presented.
Abstract: This paper presents a novel fault independent algorithm for redundancy identification (FIRE) in combinational circuits. The algorithm is based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is undetectable and hence redundant. It uses implications to find a subset of such faults whose detection requires conflicts on certain lines in the circuit. Our results on benchmark circuits indicate that we find a large number of redundancies, much faster when compared to a test-generation-based approach for redundancy identification. >

45 citations

Proceedings ArticleDOI
26 Oct 2004
TL;DR: In this article, a non-adaptive fault diagnosis technique for scan-based designs is proposed, which guarantees accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction.
Abstract: The paper introduces a new non-adaptive fault diagnosis technique for scan-based designs. The proposed scheme guarantees accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction.

44 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: The evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes.
Abstract: In this paper, we present a study of the implication based functional constraint extraction techniques to generate pseudo-functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. We analyze its impact on reducing the overkill in testing, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, we show that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, our evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes.

44 citations

Patent
29 Jul 2002
TL;DR: In this article, a method for automated generation of an extended fault tree structure adapted to a production installation or a specific installation is used within a system determining the effectiveness and analyzing causes of faults.
Abstract: A method for automated generation of an extended fault tree structure adapted to a production installation or a specific installation is used within a system determining the effectiveness and analyzing causes of faults. Generation takes place using a data processor and stored programs for carrying out functions of a hypothesis verifier, a fault data classifier, and a hypothesis configurer, and also based upon a prescribed general hierarchical fault tree structure produced by accessing data of a data server with the verifier, from which it derives fault events according to execution requirements of the verification script and stores these fault events, possibly together with previously entered fault events, in a fault database. At prescribable time intervals, the classifier carries out classification of the fault events by accessing the database, maps them as weighted causes of faults onto the tree structure, and displays or outputs the tree structure so extended.

44 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846