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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


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Patent
22 Jan 2003
TL;DR: In this article, a system and method for supporting a fault cause analysis in a fault event in a plant includes a data processor with memory storing a fault model of XML files accessed by a fault-cause navigator and an operating/display device.
Abstract: A system and method for supporting a fault cause analysis in a afault event in a plant includes a data processor with memory storing a fault model of XML files accessed by a fault cause navigator and an operating/display device. Each fault model contains an industry-specific process model divided into process steps, with steps and defined fault events needed therefor assigned to plant components/systems, and fault trees assigned to fault events and having fault hypotheses. A checklist with symptoms for verification of the fault hypothesis is assigned to the fault hypotheses. The system enables navigation to the relevant step in the process model by the display and navigator, and presents a fault event list. Following fault event selection, critical components/systems corresponding thereto are found and displayed. Possible symptoms are generated and displayed in a checklist and hypotheses of possible fault causes, contained in the fault trees, are found and displayed.

43 citations

Book ChapterDOI
10 Aug 2008
TL;DR: It is demonstrated how dynamic reconfiguration can realize a range of countermeasures which are standard for software implementations and that were practically not portable to hardware so far, and a new class of countermeasure is introduced that, to the best of the knowledge, has not been considered so far.
Abstract: Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead needed to provide reconfigurability. We show that dynamic reconfiguration can also improve the resistance of cryptographic systems against physical attacks. First, we demonstrate how dynamic reconfiguration can realize a range of countermeasures which are standard for software implementations and that were practically not portable to hardware so far. Second, we introduce a new class of countermeasure that, to the best of our knowledge, has not been considered so far. This type of countermeasure provides increased resistance, in particular against fault attacks, by randomly changing the physical location of functional blocks on the chip area at run-time. Third, we show how fault detection can be provided on certain devices with negligible area-overhead. The partial bitstreams can be read back from the reconfigurable areas and compared to a reference version at run-time and inside the device. For each countermeasure, we propose a prototype architecture and evaluate the cost and security level it provides. All proposed countermeasures do not change the device's input-output behavior, thus they are transparent to upper-level protocols. Moreover, they can be implemented jointly and complemented by other countermeasures on algorithm-, circuit-, and gate-level.

43 citations

Journal ArticleDOI
TL;DR: In this article, a new impedance-based supplementary fault-location algorithm for series capacitor-compensated transmission lines (SCCTLs) is presented, which improves the accuracy of the existing fault location algorithms.
Abstract: This paper presents a new impedance-based supplementary fault-location algorithm for series capacitor-compensated transmission lines (SCCTLs), which improves the accuracy of the existing fault-location algorithms. The proposed algorithm utilizes the fact that the metal–oxide varistor (MOV) may become bypassed in faulted or all phases before the interruption of fault for certain fault scenarios. The removal of the nonlinear element, that is, MOV from the fault loop enables the proposed algorithm to provide more accurate fault-location results compared to the most advanced impedance-based technique. Another major advantage of the proposed algorithm is that the dedicated subroutines are not required for the location of a fault in a particular section of the transmission line. The proposed fault-location algorithm is rigorously tested for various fault scenarios in the 500-kV SCCTL simulated in PSCAD. The performance of the proposed algorithm is compared to a well-known existing impedance-based fault-location algorithm for SCCTLs to illustrate higher accuracy and improved sensitivity of the proposed technique.

43 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR) together with the dynamic compaction algorithm, called MinTest.
Abstract: This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test sets generated by MinTest are 30% smaller than the previously published two-pattern test set compaction results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

43 citations

Proceedings ArticleDOI
25 Mar 1997
TL;DR: In this paper, the fault locators are used to capture the fault generated high frequency voltage or current transient signals from the faulted line/cable and the propagation time of the high frequency components is used to determine the fault position.
Abstract: Contemporary methods for fault location on overhead lines and underground cables can be classified into two fundamental types: (i) methods based on the measurement of post-fault line impedance; and (ii) methods based on the measurement of the fault generated travelling wave component. This paper presents the application of these new techniques to fault location on transmission and distribution line/cable systems. The technique utilises the specially designed fault locators to capture the fault generated high frequency voltage or current transient signals from the faulted line/cable. The propagation time of the high frequency components is used to determine the fault position.

43 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846