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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


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Journal ArticleDOI
TL;DR: The test results reveal that good performance in fault detection and fault diagnosis on both interconnect resources and CLBs can be achieved at levels similar to those required in previous works.
Abstract: This paper presents a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). The proposed FPGA BIST structure can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs. The applications on XC4000-series FPGAs show that 100% fault coverage of the proposed FPGA BIST structure can be obtained. Additionally, the test results reveal that good performance in fault detection and fault diagnosis on both interconnect resources and CLBs can be achieved at levels similar to those required in previous works.

42 citations

Journal ArticleDOI
TL;DR: This paper investigates the fault detection and isolation (FDI) problem for a class of nonlinear systems with sensor outage faults and proposes a multiple-model scheme based on the affine fuzzy model that describes the system in the presence of a specified fault.
Abstract: This paper investigates the fault detection and isolation (FDI) problem for a class of nonlinear systems with sensor outage faults. The considered nonlinear systems are described as affine fuzzy models, and the system outputs are chosen as the premise variables of fuzzy models. Different from the existing results, the influence of sensor faults on premise variables is considered. As a result, the well-known parallel distributed compensation scheme cannot be used for FDI filters design. By using the structural information encoded in the fuzzy rules, the affine fuzzy system is represented by multiple operating-regime-based models in fault-free case and faulty cases. In the multiple-model scheme, a bank of piecewise FDI filters are constructed, each of them is based on the affine fuzzy model that describes the system in the presence of a specified fault. The fault-dependent residual signals generated from the filters are used for detecting and isolating the specified fault. The FDI filter design conditions are obtained in the formulation of linear matrix inequalities. Finally, a numerical example is given to illustrate the effectiveness and merits of the proposed method.

42 citations

Journal ArticleDOI
TL;DR: It is shown how the nonlinear output regulation theory can be successfully adopted in order to design a regulator able to offset the effect of all the possible faults which can occur and, so doing, also to detect and isolate the occurred fault.

42 citations

Journal ArticleDOI
TL;DR: A method of fault signature generation is presented that is based upon state space analysis of linear circults and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits is presented.
Abstract: A method of fault signature generation is presented that is based upon state space analysis of linear circults. An input control sequence is designed to reduce a nontrivial initial state of the circuit under test to the zero state in finite time. The realization of this stimulus as a piecewise constant waveform has step amplitudes that are exponential functions of the poles of the circuit under test. Perturbations of these amplitudes, engendered by element drift failure, constitute a fault signature. Single element value perturbations engender fault signature trajectories in signal space, and the fault dictionary is constructed by defining disjoint decision regions (hypervolumes) around each fault signature trajectory in the signal space. Circuit zeros of transmission allow the dimension of the signal space to be augmented with perturbation of such response waveform parameters as zero crossings. The theory of stimulus design for fault isolation in linear networks and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits are presented. Examples of response waveforms and fault signature trajectories are given for several circuits.

42 citations

Proceedings ArticleDOI
29 Jun 2005
TL;DR: An autonomous self-repair approach for SRAM-based FPGAs is developed based on competitive runtime reconfiguration (CRR) that enables evolution of a customized fault-specific repair, realized directly as new configurations using the FPGA's normal throughput processing operations.
Abstract: An autonomous self-repair approach for SRAM-based FPGAs is developed based on competitive runtime reconfiguration (CRR). Under the CRR technique, an initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. At run-time, these individuals compete for selection based on a fitness function favoring fault-free behavior. Hence, any physical resource exhibiting an operationally-significant fault decreases the fitness of those configurations which use it. Through runtime competition, the presence of the fault becomes occluded from the visibility of subsequent FPGA operations. Meanwhile, the offspring formed through crossover and mutation of faulty and viable configurations are reintroduced into the population. This enables evolution of a customized fault-specific repair, realized directly as new configurations using the FPGA's normal throughput processing operations. Multiple phases of the fault handling process including detection, isolation, diagnosis, and recovery are integrated into a single cohesive approach. FPGA-based multipliers are examined as a case study demonstrating evolution of a complete repair for a 3-bit /spl times/ 3-bit multiplier from several stuck-at-faults within a few thousand iterations. Repairs are evolved in-situ, in real-time, without test vectors, while allowing the FPGA to remain partially online.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846