Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

AR-SMT: a microarchitectural approach to fault tolerance in microprocessors

Abstract: This paper speculates that technology trends pose new challenges for fault tolerance in microprocessors. Specifically, severely reduced design tolerances implied by gigaherz clock rates may result in frequent and arbitrary transient faults. We suggest that existing fault-tolerant techniques-system-level, gate-level, or component-specific approaches-are either too costly for general purpose computing, overly intrusive to the design, or insufficient for covering arbitrary logic faults. An approach in which the microarchitecture itself provides fault tolerance is required. We propose a new time redundancy fault-tolerant approach in which a program is duplicated and the two redundant programs simultaneously run on the processor: The technique exploits several significant microarchitectural trends to provide broad coverage of transient faults and restricted coverage of permanent faults. These trends are simultaneous multithreading, control flow and data flow prediction, and hierarchical processors-all of which are intended for higher performance, but which can be easily leveraged for the specified fault tolerance goals. The overhead for achieving fault tolerance is low, both in terms of performance and changes to the existing microarchitecture. Detailed simulations of five of the SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 10% to 30% longer than running a single version of the program.

Adaptive fault-tolerant control of nonlinear uncertain systems: an information-based diagnostic approach

Abstract: This paper presents a unified methodology for detecting, isolating and accommodating faults in a class of nonlinear dynamic systems. A fault diagnosis component is used for fault detection and isolation. On the basis of the fault information obtained by the fault-diagnosis procedure, a fault-tolerant control component is designed to compensate for the effects of faults. In the presence of a fault, a nominal controller guarantees the boundedness of all the system signals until the fault is detected. Then the controller is reconfigured after fault detection and also after fault isolation, to improve the control performance by using the fault information generated by the diagnosis module. Under certain assumptions, the stability of the closed-loop system is rigorously investigated. It is shown that the system signals remain bounded and the output tracking error converges to a neighborhood of zero.

Inductive Fault Analysis of MOS Integrated Circuits

Abstract: Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.

Test set compaction algorithms for combinational circuits

Abstract: This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

Fault Location on Power Networks

Abstract: Electric power systems will always be exposed to the failure of their components. When a fault occurs on a line, it is crucial for the fault location to be identified as accurately as possible, allowing the damage caused by the fault to be repaired quickly before the line is put back into service. Fault Location on Power Lines enables readers to pinpoint the location of a fault on power lines following a disturbance. If a fault location cannot be identified quickly and this causes prolonged line outage during a period of peak load, severe economic losses may occur and reliability of service may be questioned. The growth in size and complexity of power systems has increased the impact of failure to locate a fault and therefore heightened the importance of fault location research studies, attracting widespread attention among researchers in recent years. Fault location cannot be truly understood, applied, set, tested and analysed without a deep and detailed knowledge of the interiors of fault locators. Consequently, the nine chapters are organised according to the design of different locators. The authors do not simply refer the reader to manufacturers documentation, but instead have compiled detailed information to allow for in-depth comparison. Fault Location on Power Lines describes basic algorithms used in fault locators, focusing on fault location on overhead transmission lines, but also covering fault location in distribution networks. An application of artificial intelligence in this field is also presented, to help the reader to understand all aspects of fault location on overhead lines, including both the design and application standpoints. Professional engineers, researchers, and postgraduate and undergraduate students will find Fault Location on Power Lines a valuable resource, which enables them to reproduce complete algorithms of digital fault locators in their basic forms.