Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
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28 Sep 1999TL;DR: In this paper, a defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment, where CMOS resistive vias and contacts were used as a delay defect target.
Abstract: This defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment. Delay fault testing has uncertainty, or noise, in its attempt to detect defects that slow a signal. CMOS resistive vias and contacts were used as a delay defect target. Data were taken from a scan-based test chip (Veqtor) on the Philips 0.25 /spl mu/m technology. Methods to improve delay fault defect detection are given.
127 citations
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TL;DR: Proposals to further accelerate fault simulation and fault grading aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit.
Abstract: The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.
126 citations
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TL;DR: Implementation of the fault detection and of the fully digital control schemes on a single FPGA is realized, based on a suited methodology for rapid prototyping, and the results confirm the capability of the proposed reconfigurable control and fault-tolerant structure.
Abstract: In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital control schemes on a single FPGA is realized, based on a suited methodology for rapid prototyping. FPGA in loop and also experimental tests are carried out, and the results are presented. These results confirm the capability of the proposed reconfigurable control and fault-tolerant structure.
125 citations
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TL;DR: The main vehicle of this approach is the deduction of internal line values in a circuit under test N*.
Abstract: In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.
125 citations
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12 Oct 2003TL;DR: In this article, the authors proposed a method for detecting bearing faults via stator current, which is robust to many influences including variations in supply voltage, cyclical load torque variations, and other (nonbearing) fault sources.
Abstract: This research proposes a method for detecting developing bearing faults via stator current Current-based condition monitoring offers significant economic savings and implementation advantages over vibration-based techniques This method begins by filtering the stator current to remove most of the significant frequency content unrelated to bearing faults Afterwards, the filtered stator current is used to train an autoregressive signal model This model is first trained while the bearings are healthy, and a baseline spectrum is computed As bearing health degrades, the modeled spectrum deviates from its baseline value; the mean spectral deviation is then used as the fault index This fault index is able to track changes in machine vibration due to developing bearing faults Due to the initial filtering process, this method is robust to many influences including variations in supply voltage, cyclical load torque variations, and other (nonbearing) fault sources Experimental results from 10 different bearings are used to verify the proficiency of this method
125 citations