Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
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10 Feb 2007TL;DR: This paper presents an idealized algorithm capable of identifying over 85% of injected faults on the SpecInt suite and over 75% overall and shows that flushing the pipeline every time the hardware screener triggers reduces overall performance by less than 1%.
Abstract: Fault screeners are a new breed of fault identification technique that can probabilistically detect if a transient fault has affected the state of a processor. We demonstrate that fault screeners function because of two key characteristics. First, we show that much of the intermediate data generated by a program inherently falls within certain consistent bounds. Second, we observe that these bounds are often violated by the introduction of a fault. Thus, fault screeners can identify faults by directly watching for any data inconsistencies arising in an application's behavior. We present an idealized algorithm capable of identifying over 85% of injected faults on the SpecInt suite and over 75% overall. Further, in a realistic implementation on a simulated Pentium-III-like processor, about half of the errors due to injected faults are identified while still in speculative state. Errors detected this early can be eliminated by a pipeline flush. In this paper, we present several hardware-based versions of this screening algorithm and show that flushing the pipeline every time the hardware screener triggers reduces overall performance by less than 1%
115 citations
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115 citations
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TL;DR: In this paper, the voltage sags produced by balanced and unbalanced short circuits are analyzed by means of a new analytical method, which does not require a pre-assignation of discrete fault positions along the lines.
Abstract: In this paper, voltage sags produced by balanced and unbalanced short circuits are analyzed by means of a new analytical method. The main feature of this approach is that contrary to the fault positions method, it does not require a preassignation of discrete fault positions along the lines. The developed algorithm has been applied to the 24-buses IEEE Reliability Test System (RTS) and to a real transmission system to illustrate its application. Results are analyzed and compared with the fault positions method. The mathematical formulation of the proposed approach is straightforward and different fault distributions along the lines can be effortlessly considered. The proposed method is adequate for the analysis of any size networks.
115 citations
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TL;DR: A residual generator based on the Kalman filter is proposed, which can be used to detect if a failure occurs and two Kalman filters are designed to diagnose the fault type.
Abstract: In this paper, we consider the fault diagnosis and fault-tolerant problem for a linear drive system subject to system noise. First, we propose a residual generator based on the Kalman filter, which can be used to detect if a failure occurs. Second, two Kalman filters are designed to diagnose the fault type. Third, when a fault is diagnosed, the fault-tolerant control is used to accommodate this failure. Finally, the proposed method is tested in a real linear drive system.
115 citations
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TL;DR: A new representation for faults in combinational digital circuits is presented, where faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments.
Abstract: A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs.
114 citations