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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


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Journal ArticleDOI
TL;DR: In this article, the authors used the telegraph equations as a line model, voltage and current samples taken at one end of a line within the first 5 ms of fault inception are used to generate instantaneous voltage and currents profiles for the rest of the transmission line.
Abstract: The high frequency components in fault waveforms present undesirable effects to most fault location algorithms and as a consequence filtering of postfault signals, to remove the high frequency transients, is essential for accurate fault location. A fault location algorithm that derives from travelling wave principles can cope with high frequency transients since these basically depend on travelling wave phenomena. The development of such an algorithm is the objective of this paper. Using the telegraph equations as a line model, voltage and current samples taken at one end of a line within the first 5 ms of fault inception are used to generate instantaneous voltage and current profiles for the rest of the transmission line. The voltage and current estimation is based on the solution of the equations of the line model by the method of characteristics. Criteria functions involving any of the square of the voltage, the square of the current, or the product of the two are applied for determination of the fault position. Fault position is given by the peak variation in tangent to the above basic functions. The algorithm finds application in fault location on two and three-terminal networks at both transmission and distribution levels.

101 citations

Journal ArticleDOI
TL;DR: A method for identifying the X inputs of test vectors in a given test set by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms is proposed.
Abstract: Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit, some of the primary input values may be changed to the opposite logic values without losing fault coverage. We can regard such input values as don't care (X). In this paper, we propose a method for identifying the X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including as many X inputs as possible, by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms. Experimental results for ISCAS benchmark circuits show that approximately 69% of the inputs of uncompacted test sets could be X on the average. Even for highly compacted test sets, the method found that approximately 48% of inputs are X.

101 citations

Journal ArticleDOI
TL;DR: In this article, the fault diagnosis problem for a class of non-linear systems with uncertainty which depends on states, inputs and unknown constant parameters is discussed, where the system is transformed into two different subsystems.
Abstract: In this paper, the fault diagnosis problem for a class of non-linear systems with uncertainty which depends on states, inputs and unknown constant parameters is discussed. Under some geometric conditions, the system is transformed into two different subsystems. One is not affected by actuator faults, so a non-linear adaptive observer can be designed based on the assumption of the strictly positive realness (SPR). The other whose states can be measured is affected by the faults. Actuator fault diagnosis is based on estimations of both the state and the unknown parameters with good accuracy. Discussions on release of SPR requirement and extension to the sensor fault case are also made. Finally, two examples are given in order to illustrate the applicability of the proposed methods for actuator fault diagnosis and sensor fault diagnosis respectively.

100 citations

Book
01 Jan 1998
TL;DR: This work implements the 1149.4 Standard Mixed-Signal Test Bus with a focus on the integration of Behavioral Modeling into Fault Simulation, and aims to demonstrate the benefits of using this Standard on an IC.
Abstract: List of Figure. List of Tables. Preface. Contributors. 1. Introduction. Motivation. History. Current Research. Influence of Digital Test. Analog Test Issues. Test Paradigms. Organization. Conclusion. 2. Defect-Oriented Testing. Introduction. Previous Work. Estimation Method. Topological Method. Taxonomical Method. Defect-Based Realistic Fault Dictionary. Implementation. A Case Study. Fault Matrix Generation. Stimuli Matrix. Simulation Results. Silicon Results. Observations and Analysis. IFA-based Fault Grading and DFT for Analog Circuits. A/D Converter Testing. Description of the Experiment. Fault Simulation Issues. Fault Simulation Results. Analysis. DFT Measures. High-Level Analog Fault Models. Discussion: Strengths and Weaknesses of IFA-Based Tests. 3. Fault Simulation. Introduction. Why Analog Fault Simulation? Analog Fault Models and What-if Analysis. Focus and Organization. Fault Simulation of Linear Analog Circuits. Householder's Formula. Discrete Z-domain Mapping. Fault Bands and Band Faults. Interval-Mathematics Approach. Summary. C Fault Simulation of Nonlinear Analog Circuits. The Complementary Pivot Method. Fault Simulation via One-Step Relaxation. Simulation by Fault Ordering. Handling Statistical Variations. Summary. Fault Co-Simulation with Multiple Levels of Abstraction. Mixed-Signal Simulators. Incorporating Behavioral Models in Fault Simulation. Fault Macromodeling and Induced Behavioral Fault Modeling. Statistical Behavioral Modeling. Remarks on Hardware Description Languages. Concluding Remarks. 4. Automatic Test Generation Algorithms. Introduction. Fundamental Issues in Analog ATPG. Structural Test Versus Functional Test. Path Sensitization. Measurement Impact on Test Generation. Simulation Impact on Test Generation. Test Generation Algorithms and Results. Functional Test Generation Algorithms. Structural Test Generation Algorithms. ATPG Based on Automatic Test Selection Algorithms. DFT-based Analog ATPG Algorithms. Conclusions. 5. Design for Test. Preliminaries. Analog Characteristics. Common Characteristics. Generic Test Techniques. Increased Controllability/Observability. A/D Boundary Control. System-Specific Test Techniques. Analog Scan. Boundary Scan. Macro-Based DFT. Operational Amplifiers. Data Converters. Filters. Quality Analysis. Preliminaries. Analysis. Analysis. Conclusion. 6. Spectrum-Based Built-in Self-Test. Introduction. Some Early BIST Schemes. On-Chip Signal Generation. Digital Frequency Synthesis. Delta-Sigma Oscillators. Fixed-Length Periodic Bit Stream. Parameter Analysis. Fast Fourier Transform. Sinewave Correlation. Bandpass Filters. Application: MADBIST. Baseband MADBIST. Baseband MADBIST Experiments. MADBIST for Transceiver Circuits. Conclusions and Future Directions. 7. Implementing the 1149.4 Standard Mixed-Signal Test Bus. Overview of 1149.1 and 1149.4186. Test Functions Needed to Implement 1149.4189. Test Capabilities That This Standard Facilitates. Resistance, Capacitance, and Inductance Measurement. Measuring DC Parameters of Inputs and Outputs. Differential Measurements. Bandwidth. Delay Measurement. Potential Benefits of Using This Standard. Costs of Implementing This Standard on an IC. Practical Circuits Compliant with the Standard (Draft 18). Achieving Measurement Accuracy. DC Measurement Errors. AC Measurement Errors. Noise. Lessons from Test ICs. IMP (International Microelectronics Products) IC. Matsushita IC. Conclusions. 8. Test Techniques for CMOS Switched-Current Circuits. Introduction. Current Copiers: Basic Building Blocks of SI Circuits. Structure and Operation. Testing Current Copiers. Testing of Switched-Current Algorithmic A/D Converters. Structure and Operation. Concurrent Error Detection (CED). Test Generation. BIST Design. Scan Structures: Design for Testability. Conclusion. Index.

100 citations

Journal ArticleDOI
TL;DR: The Poirot tool isolates and diagnoses defects through fault modeling and simulation, and functional and sequential test pattern applications show success with circuits having a high degree of observability.
Abstract: The Poirot tool isolates and diagnoses defects through fault modeling and simulation. Along with a carefully selected partitioning strategy, functional and sequential test pattern applications show success with circuits having a high degree of observability.

100 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846