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Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.


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Proceedings ArticleDOI
22 Jan 1996
TL;DR: The work to date shows a substantial improvement in computational effort for large, complex fault trees analysed with this method in comparison to the traditional approach, and some ways in which it can be efficiently implemented on a computer.
Abstract: Fault tree analysis is now commonly used to assess the adequacy, in reliability terms, of industrial systems. For complex systems, an analysis may produce thousands of combinations of events which can cause system failure (minimal cut sets). The determination of these minimal cut sets can be a very time consuming process even on modern high speed digital computers. Also, if the fault tree has many minimal cut sets, calculating the exact top event probability will require extensive calculations. For many complex fault trees this requirement is beyond the capability of the available machines, thus approximation techniques need to be introduced resulting in loss of accuracy. This paper describes the use of a binary decision diagram for fault tree analysis and some ways in which it can be efficiently implemented on a computer. The work to date shows a substantial improvement in computational effort for large, complex fault trees analysed with this method in comparison to the traditional approach. The binary decision diagram method has the additional advantage that as approximations are not required, exact calculations for the top event parameters can be performed.

93 citations

Proceedings ArticleDOI
07 Nov 1993
TL;DR: This simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits with the help of hierarchical fault models for parametric and catastrophic faults and a very efficient fault simulator.
Abstract: Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

93 citations

Proceedings ArticleDOI
26 Oct 1991
TL;DR: A fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's is introduced and a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.
Abstract: The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.

93 citations

Journal ArticleDOI
TL;DR: In this paper, a novel method for the detection of high-impedance faults is proposed which uses the incremental variance of a normalized even order ratio measure, based on which three criteria, (even-order power, even-order ratio, and evenorder incremental variance) for fault detection are presented, all of which are based on the changes of normalized evenorder harmonic power in fault currents.
Abstract: A novel method for the detection of high-impedance faults is proposed which uses the incremental variance of a normalized even order ratio measure. Staged fault tests were extensively carried out in Korean electric power systems. From the analysis of the staged fault test data, it was found that there exists an intermittent arcing phenomenon in most high-impedance faults and that the waveforms of this arcing fault current have an asymmetrical shape in each cycle. Based on these facts, three criteria, (even-order power, even-order ratio, and even-order incremental variance) for fault detection are presented, all of which are based on the changes of normalized even-order harmonic power in fault currents. These criteria are compared through the analysis of staged fault data and normal switching event data. It is shown that the even-order incremental variance criterion is superior to the other two criteria and that, with this criterion, high-impedance faults can be distinguished from normal switching events, including special loads such as electric furnaces and subways. Microprocessor-based protective relays, which can detect high-impedance faults by using the proposed methods, have been constructed, installed in Korea Electric Power Corporation substations, and tested during the last two years. Details of these field tests are given. >

93 citations

Proceedings ArticleDOI
Y. Sato1, L. Yamazaki1, H. Yamanaka1, T. Ikeda1, M. Takakura 
07 Oct 2002
TL;DR: A technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed, and some experimental results of actual chips are shown.
Abstract: We present a persistent diagnostic technique for unstable defects, such as open defects or delay defects. A new "segment model" diagnosis for the completely open defects is discussed. Here, we not only focus on the behavior of the principal offender, but also the behavior of the accomplices which cause the unstable behavior of the defect. In this paper, a technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed. Some experimental results of actual chips are shown.

92 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202336
202298
20219
20206
20199
201846