Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

On innovative methods of induction motor interturn and broken-bar fault diagnostics

Abstract: A fault indicator, the so-called swing angle, for broken-bar and interturn faults is investigated in this paper. This fault indicator is based on the rotating magnetic-field pendulous-oscillation concept in faulty squirrel-cage induction motors. Using the "swing-angle indicator," it will be demonstrated here that an interturn fault can be detected even in the presence of machine manufacturing imperfections. Meanwhile, a broken-bar fault can be detected under both direct-line and PWM excitations, even under the more difficult condition of partial-load levels. These two conditions of partial load and motor manufacturing imperfections, which are considered as difficult situations for fault detection, are investigated through experimentally obtained test results for a set of 2- and 5-hp induction motors.

Accurate Single-Phase Fault-Location Method for Transmission Lines Based on K-Nearest Neighbor Algorithm Using One-End Voltage

Abstract: In this paper, some useful features are extracted from voltage signals measured at one terminal of the transmission line, which are highly efficient for accurate fault locating. These features are the amplitude of harmonic components, which are extracted after fault inception through applying discrete Fourier transform on one cycle of three-phase voltage signals and then are normalized by a transformation. In this paper, the location of single-line-to-ground faults as the most probable type of fault in the transmission networks is considered. The SLG fault locator, which is designed based on the simple algorithm of k-nearest neighbor (k-NN) in regression mode, estimates the location of fault related to the new input pattern based on existing available patterns. The proposed approach only needs the measured data from one terminal; hence, data communication between both ends of the line and synchronization are not required. In addition, current signals are not used; therefore, the proposed approach is immune against current-transformer saturation and its related errors. Tests conducted on an untransposed transmission line indicate that the proposed fault locator has accurate performance despite simultaneous changes in fault location, fault inception angle, fault resistance, and magnitude and direction of load current.

Implicit test generation for behavioral VHDL models

Abstract: This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.

Testing delay-insensitive circuits

Abstract: A method is developed to test delay-insensitive circuits, using the single stuck-at fault model. These circuits are synthesized from a high-level specification. Since the circuits are hazard-free by construction, there is no test for hazards in the circuit. Most faults cause the circuit to halt during test, since they cause an acknowledgement not to occur when it should. There are stuck-at faults that do not cause the circuit to halt under any condition. These are stimulating faults; they cause a premature firing of a production rule. For such a stimulating fault to be testable, the premature firing has to be propagated to a primary output. If this is not guaranteed to occur, then one or more test points have to be added to the circuit. Any stuck-at fault is testable, with the possible addition of test points. For combinational delay-insensitive circuits, finding test vectors is reduced to the same problem as for synchronous combinational logic. For sequential circuits, the synthesis method is used to find a test for each fault efficiently, to find the location of the test points, and to find a test that detects all faults in a circuit. The number of test points needed to fully test the circuit is very low, and the size of the additional testing circuitry is small. A test derived with a simple transformation of the handshaking expansion yields high fault coverage. Adding tests for the remaining faults results in a small complete test for the circuit.