Topic
Stuck-at fault
About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.
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03 May 1992
TL;DR: The evolution of accurate fault models, especially with respect to integrated circuit diagnosis, are described and the solution to the Byzantine General's problem is described using the voting model for CMOS bridging faults.
Abstract: This paper describes the evolution of accurate fault models, especially with respect to integrated circuit diagnosis. The difference between accuracy and precision is described. The solution to the Byzantine General's problem is described using the voting model for CMOS bridging faults.
82 citations
06 May 2014
TL;DR: This paper presents a survey on the simulation-based fault injection techniques, with a focus on complex micro-processor based systems.
Abstract: Dependability is a key decision factor in today's global business environment. A powerful method that permits to evaluate the dependability of a system is the fault injection. The principle of this approach is to insert faults into the system and to monitor its responses in order to observe its behavior in the presence of faults. Several fault injection techniques and tools have been developed and experimentally tested. They could be mainly grouped into three categories: hardware fault injection, simulation-based fault injection, and emulation-based fault injection. This paper presents a survey on the simulation-based fault injection techniques, with a focus on complex micro-processor based systems.
82 citations
01 Jul 1992
TL;DR: Three new techniques that substantially speed up parallel fault simulation are proposed: reduction of faults simulated in parallel through mapping nonstem faults to stem faults, a new fault injection method called functional fault injection, and a combination of a static fault ordering method and a dynamic fault orders method.
Abstract: HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.
81 citations
TL;DR: A novel topology of multilevel inverter is proposed that can tolerate both open and short-circuit faults on its switches and also reduces dc sources and capacitors as compared to the conventional and recently proposed fault-tolerant topologies.
Abstract: Low reliability is one of the major concerns of multilevel inverter due to the requirement of a large number of semiconductor devices as compared to two-level inverters. Thus, in this paper, a novel topology of multilevel inverter is proposed that can tolerate both open and short-circuit faults on its switches. The proposed topology also reduces dc sources and capacitors as compared to the conventional and recently proposed fault-tolerant topologies. Two types of solutions are provided in order to make the proposed topology fault tolerant; first provides a partial solution to fault, while the second provides a complete solution to fault. In addition, a novel switching strategy is proposed to reduce the amount of capacitor voltage ripples under normal and postfault conditions. Also, the proposed switching scheme offers an additional advantage of self-voltage balancing of its capacitor voltage both under normal as well as postfault conditions. To validate the proposed concepts, simulation and experimental analysis are carried out and different results are presented to show the viability of the proposed topology under normal operation, during fault and postfault conditions.
81 citations
TL;DR: In this paper, a fault transient detector unit at the relaying point is used to capture fault generated high frequency transient signals contained in the primary currents, and the decision to trip is based on the relative arrival times of these high frequency components as they propagate through the system.
Abstract: This paper presents a new technique for high-speed protection of transmission lines, the positional protection technique. The technique uses a fault transient detector unit at the relaying point to capture fault generated high frequency transient signals contained in the primary currents. The decision to trip is based on the relative arrival times of these high frequency components as they propagate through the system. Extensive simulation studies of technique were carried out to examine the response to different power system and fault conditions. Results show that the scheme is insensitive to fault type, fault resistance, fault inception angle and system source configuration, and that it is able to offer both very high accuracy and speed in fault detection.
81 citations