Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

An accurate fault classification technique for power system monitoring devices

Abstract: This paper presents a novel method of classifying transmission line shunt faults. Most algorithms that are employed for analyzing fault data require that the fault type be classified. The older fault type classification algorithms are inefficient because they are not effective under certain operating conditions of the power system and may not be able to accurately select the faulted transmission line if the same fault recorder monitors multiple lines. The technique described in this paper has been proven to accurately identify all ten types of shunt faults that may occur in an electric power transmission system. The other advantage of this technique is that it can be used where multiple transmission lines are present. It is able to identify the faulted line even if secondary effects are recorded in the unfaulted lines.

On behavior fault modeling for digital designs

Abstract: A critical aspect of digital electronics is the testing of the manufactured designs for correct functionality. The testing process consists of first generating a set of test vectors, then applying them as stimuli to the manufactured designs, and finally comparing the output response with that of the desired response. A design is considered acceptable when the output response matches the desired response and is rejected otherwise. Fundamental to the process of test vector generation is the assumption of an underlying fault model that is a model of the failures introduced during manufacture. The choice of the fault model influences the accuracy of testing and the computer CPU time required to generate test vectors for a given design. The most popular fault model in the industry today is the single stuck-at fault at the gate level that requires exorbitantly large CPU times for moderately complex digital designs. This article introduces new high-level behavior fault models that are associated with high-level hardware descriptions of digital designs. The derivation of these faults is based on the failure modes of the language constructs of the high-level hardware description language. Behavior faults include multiple input stuck-at faults and this article also reasons the nature of test vectors for such faults. The potential advantages of behavior fault modeling include early estimates of fault coverage in the design process prior to the synthesis of the gate-level representation of the design, faster fault simulation, and results that may be more comprehensible to the high-level architects. The behavior-fault-modeling approach is evaluated through a study of correlation of the results of behavior fault simulation of several representative digital designs with the results of gate-level single stuck-at fault simulation of equivalent gate-level representations.

Integration of fault detection with run-to-run control

Abstract: Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. in these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.

Synchrophasor-Based Wide-Area Backup Protection Scheme with Data Requirement Analysis

Abstract: This paper presents a fast and robust wide-area backup protection scheme to detect the faulty condition and to identify the faulted line in a large power network The proposed methodology uses positive-sequence synchrophasor data captured by either digital relays with synchronization capability or phasor measurement units dispersed over the network The basic idea behind the new protection scheme is the comparison of bus voltage values calculated through dissimilar paths Upon occurrence of a fault, the faulty condition is first detected and the bus(es) connected to the faulted line is(are) determined Among transmission lines connected to the suspected bus(es), the faulted one is thereafter identified In addition to two-terminal transmission lines, multiterminal lines are also incorporated The performance of the proposed method is validated on the IEEE 57-bus test system in different fault conditions (fault type, fault location, and fault resistance) Discrimination of faulty and normal conditions is simulated by examining various stressed conditions, for example, load encroachment, generator outage, and power swing The data requirement of the proposed technique is analyzed as well To do so, a mathematical model for the optimal placement of measurement devices is developed and applied to different IEEE standard test systems

Fault diagnosis in scan-based BIST using both time and space information

Abstract: A new technique for diagnosis in a scan-based BIST environment is presented. It allows non-adaptive identification of both the scan cells that capture errors (space information) as well as a subset of the failing test vectors (time information). Having both space and time information allows a faster and more precise diagnosis. Previous techniques for identifying the failing test vectors during BIST have been limited in the multiplicity of errors that can be handled and/or require a very large hardware overhead. The proposed approach, however, uses only two cycling registers at the output of the scan chain to accurately identify a subset of the failing BIST test vectors. This is accomplished using some novel pruning techniques that efficiently extract information from the signatures of the cycling registers. While not all the failing BIST test vectors can be identified, results indicate that a significant number of them can be. This additional information can save a lot of time in failure analysis.