Stuck-at fault

About: Stuck-at fault is a research topic. Over the lifetime, 9707 publications have been published within this topic receiving 160254 citations.

A method of delay fault test generation

Abstract: It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path, FTP, and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [1]. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task.

An accurate bridging fault test pattern generator

Abstract: Test pattern generation for bridging faults has been considered impractical. This paper presents an accurate bridging fault test pattern generator Lhat requires only a gate-level implementation of the circuit. No transistorlevel simulations are required during test pattern generation. Results presented for the ISCAS'85 benchmark circuits indicate that this test pattern generator is 8 practical solution to a problem that must be solved in order to detect the failures that occur in modern VLSI circuits.

Optimal test set design for analog circuits

Abstract: Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

An architecture for fault tolerant controllers

Abstract: A general architecture for fault tolerant control is proposed. The architecture is based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBK parameterization to quantify the performance of the fault tolerant system. The approach suggested can be applied for additive faults, parametric faults and for system structural changes. The modelling for each of these fault classes is described. The method allows for design of passive as well as for active fault handling. Also, the related design method can be fitted either to guarantee stability or to achieve graceful degradation in the sense of guaranteed degraded performance. A number of fault diagnosis problems, fault tolerant control problems, and feedback control with fault rejection problems are formulated/considered, mainly from a fault modelling point of view. The method is illustrated on a servo example including an additive fault and a parametric fault.