About: Substrate coupling is a research topic. Over the lifetime, 1504 publications have been published within this topic receiving 25219 citations.
Papers published on a yearly basis
TL;DR: In this paper, a patterned ground shield is inserted between an on-chip spiral inductor and silicon substrate to increase the quality of a 2 GHz LC tank by up to 33% and reduce substrate coupling between two adjacent inductors.
Abstract: This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor.
TL;DR: In this paper, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. But the authors did not consider the effect of the layout geometry of the substrate.
Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >
•03 Sep 1999
TL;DR: In this article, an interposer is used to attach an integrated circuit (116) to the antenna elements (112, 114), which reduces the precision required to successfully couple the integrated circuit to the antennas elements.
Abstract: A radio frequency identification tag (100) includes a substrate member (110) having an inner surface and an outer surface. Disposed on the inner surface are first (112) and second (114) antenna elements. The antenna elements are electrically isolated from each other and coupled to two separate pads on an integrated circuit (116). Adhesive (118) is applied on the inner surface of the substrate, the antenna elements and the integrated circuit for securing the tag. The tag may employ an interposer (600) to attach integrated circuit (116) to the antenna elements (112, 114). The interposer (600) has a substrate (602) and first and second connecting pads (602, 604) electrically isolated from each other and electrically connected to the connecting pads on the integrated circuit (116). Interposer (600) reduces the amount of the precision required to successfully couple integrated circuit (116) to the antenna elements (112, 114).
TL;DR: In this article, a planar negative coupling scheme including a magnetic coupling post-wall iris and a balanced microstrip line with a pair of metallic via-holes is studied in detail.
Abstract: Substrate integrated waveguide (SIW) technology provides an attractive solution to the integration of planar and nonplanar circuits by using a planar circuit fabrication process. However, it is usually difficult to implement the negative coupling structure required for the design of compact canonical folded elliptic or quasi-elliptic cross-coupled bandpass filter on the basis of a single-layer SIW. In this paper, a special planar negative coupling scheme including a magnetic coupling post-wall iris and a balanced microstrip line with a pair of metallic via-holes is studied in detail. Two -band fourth-degree cross-coupled bandpass filters without and with source-load coupling using the negative coupling structures are then proposed and designed. The two novel SIW filters having the same center frequency of 20.5 GHz and respective passband width of 700 and 800 MHz are implemented on a single-layer Rogers RT/Duroid 5880 substrate with thickness of 0.508 mm. Measured results of those filters, which exhibit a high selectivity, and a minimum in-band insertion loss of approximately 0.9 and 1.0 dB, respectively, agree well with simulated results.
TL;DR: In this paper, the authors analyzed both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compared them to those of normal bulk CMOS process.
Abstract: This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.