Showing papers on "Substrate (electronics) published in 1987"

Electron Spectroscopy Studies on Magneto-Optical Media and Plastic Substrate Interface

Abstract: The depth-profiles of amorphous TbFeCo films sputtered onto polycarbonate substrate were studied by X-ray photoelectron spectroscopy. Oxidized metals, oxides and hydroxides for example, and adsorbed impurities were found to exist mainly in the vicinity of the film surface and film/ substrate interface.

Extreme selectivity in the lift‐off of epitaxial GaAs films

Abstract: We have discovered conditions for the selective lift‐off of large area epitaxial AlxGa1−xAs films from the substrate wafers on which they were grown. A 500‐A‐thick AlAs release layer is selectivity etched away, leaving behind a high‐quality epilayer and a reusable GaAs substrate. We have measured a selectivity of ≳107 between the release layer and Al0.4Ga0.6As. This process relies upon the creation of a favorable geometry for the outdiffusion of dissolved H2 gas from the etching zone.

Porosity and Pore Size Distributions of Porous Silicon Layers

Abstract: Porosities of porous silicon layers formed on different types of substrates and under different experimental conditions are compared with and related to the pore size distribution determined by gas adsorption experiments. Results show that porous layers formed on lightly P-doped silicon exhibit a network of very narrow pores, of radii less than 2 nm. Porous films formed on heavily doped silicon present larger radii, ranging between 2 and 9 nm according to the experimental conditions. Larger porosities and larger pore sizes are obtained by increasing the forming current density or by decreasing the HF concentration. Heavily P-doped porous silicon layers are homogeneous in depth and generally present a quite sharp pore size distribution. With heavily N-doped silicon, an increase in porosity with increasing thickness is found, which corresponds to an increase in pore size, leading to a broadening of size distributions. This porosity gradient is attributed to a chemical dissolution of the layer occurring during anodization. In addition, a strong dependence of porosity with small variations in doping level is found. Porous silicon is a material obtained by anodic oxidation of monocrystalline silicon in concentrated hydrofluoric acid solutions. Several papers (1-4) have shown that this material is one of the promising candidates for use in silicon on insulator (SOI) structures in integrated circuit technology. In all the proposed applications, the oxidation properties of porous silicon are used to obtain thick insulating layers of silica in relatively short periods of time. The properties of the material are very dependent on the type and resistivity of the original silicon substrate and on the electrochemical parameters used during the anodization processes. Porous silicon is often characterized by its porosity, mainly due to the existence of a so-called optimal porosity of about 56%, for which good silicon dioxides are obtained with minimum strains and volume expansion (5), which is necessary to obtain fully oxidized structures. However, porosity values alone are not enough to characterize the material as quite different properties can be obtained for materials of the same porosity if the substrate resistivity and preparation conditions are properly chosen. Other parameters to be considered when a better characterization of porous structures is required are pore size and pore size distribution. Both porosity and pore size determine altogether the size of the silicon walls in the porous material, so that properties like crystalline quality (6), optical response (7), thermal behavior (8), and oxidation mechanism (9) are very dependent on both porosity and pore size. It has been shown in a previous paper (10) that it was possible using gas adsorption techniques to determine accurately the pore size and pore distribution of radii in the porous silicon layers. That work was limited to porous silicon layers prepared on (111) heavily P-doped substrates. The aim of the present work is to study (100) substrates and investigate other kinds of resistivity and different electrochemical preparation conditions. Experimental

Non-volatile memory cell having Si rich silicon nitride charge trapping layer

Abstract: A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Fabricating a semiconductor device with low defect density oxide

Abstract: Low defect density oxides suitable for use as thin gate oxides or in charge storage capacitors are described. First and second layers are formed on a substrate with misaligned defect structures. A third layer is then grown by diffusing a species through the first and second layers to the substrate. The species reacts with the substrate. The low defect density results from the misaligned defect structure of the first and second layers. In one embodiment, the first and second layers are grown and deposited oxides, respectively. The third layer is grown by diffusing oxygen through the first two layers and the interface between the first and second layers acts as a sink trapping defects. The oxide silicon interface has desirable characteristics because the oxide grows in near equilibrium conditions.

Epitaxial growth and electric characteristics of cubic SiC on silicon

Abstract: Single crystals of cubic SiC were heteroepitaxially grown by chemical vapor deposition (CVD) using a SiH4‐C3H8‐H2 system on silicon substrates. To reduce the large lattice mismatch between cubic SiC and silicon, a buffer layer was made by carbonizing the surface of a Si substrate in the CVD system. An optimum condition for the buffer layer formation was determined by x‐ray rocking curve measurements, reflection electron diffraction, and Auger electron spectroscopy. Electrical properties of the epitaxial cubic SiC layer were measured, and the mobilities on the Si(111) substrate were found to be larger than those on the Si(100) substrate. Diode characteristics of epitaxially grown p‐n junctions were also investigated.

Multilayer ceramics from hydrogen silsesquioxane

Abstract: This invention related to materials produced by diluting in a solvent a hydrogen silsesquioxane resin solvent solution which is applied to a substrate and ceramified by heating. One or more ceramic coatings containing silicon carbon, silicon nitrogen, or silicon carbon nitrogen can be applied over the ceramified SiO₂ coating. A CVD or PECVD top coating can be applied for further protection. The invention is particularly useful for coating electronic devices.

Substrate‐orientation dependence of GaN single‐crystal films grown by metalorganic vapor‐phase epitaxy

Abstract: Gallium‐nitride single crystals were grown on (0001)‐ and (0112)‐oriented sapphire substrates by metalorganic vapor‐phase epitaxy. Smooth‐surfaced layers with fine ridgelike facets can be obtained on the (0112) sapphire. They have lower carrier concentrations than the layers on the (0001) sapphire. Deep centers responsible for blue (∼425 nm) and yellow (∼560 nm) emissions from undoped layers are reduced on the (0112) substrates, as compared with the (0001) substrates. On the other hand, the layers on the (0001) sapphire have better crystallinity and higher Zn‐incorporation efficiency than those on the (0112) sapphire. Growth kinetics of GaN layers are discussed by developing a tentative model.

The growth of diamond in microwave plasma under low pressure

Abstract: The synthesis of diamond particles in a low pressure plasma has been studied, with emphasis on the investigation of the substrate effect and the plasma conditions. It was found that a special pre-treatment of silicon substrate made it possible to form dense films, and a thickness of about 15μm could be reached by 20 h discharge. Unfortunately, however, the prepared films had poor adhesion. Observations by scanning electron microscope (SEM) showed that the poor adhesion was due to the fact that the film consisted of large particles with a diameter of about 10μm, and each particle had contacted to the substrate only by a point, not by a face. In addition, the plasma diagnostics of optical and ultraviolet emission spectroscopy (OES, 200–750 nm) revealed that CH and H radicals have come to be criteria for the formation of diamonds, and the ratio of radicals drastically affected the characteristics of the deposits. Nucleation and growth mechanism are also discussed.

Trench sidewall isolation by polysilicon oxidation

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner is formed on all trench surfaces. A conformal layer of undoped polysilicon is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contract through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

Multilayer ceramic coatings from silicate esters and metal oxides

Abstract: This invention relates to materials produced by diluting in a solvent a preceramic mixture of a partially hydrolyzed silicate ester and a metal oxide precursor selected from the group consisting of an aluminum alkoxide, a titanium alkoxide, and a zirconium alkoxide. The preceramic mixture solvent solution is applied to a substrate and ceramified by heating. One or more ceramic coatings containing silicon carbon, silicon nitrogen, or silicon carbon nitrogen can be applied over the ceramified SiO₂/metal oxide coating. A CVD or PECVD top coating can be applied for further protection. The invention is particularly useful for coating electronic devices.

Initial stages of epitaxial growth of GaAs on (100) silicon

Abstract: Direct observations of early stages of molecular‐beam epitaxial growth of GaAs on oriented and vicinal (100) Si surfaces are presented. Cross‐sectional transmission electron microscopy and plan view scanning electron microscopy images directly reveal three‐dimensional island growth for substrate temperatures above 300 °C. Island size, island spacing, surface morphology, and stacking fault defect spacing all increase with substrate temperature for fixed Ga and As fluxes. Below 300 °C, 7‐nm‐thick films are continuous and uniform. Films deposited on surfaces tilted from (100) coalesce anisotropically with respect to the tilt axis.

Polysilicon thin film process

Abstract: Polycrystalline silicon is deposited in a film onto the surface of a substrate which has been carefully prepared to eliminate any defects or contaminants which could nucleate crystal growth on the substrate. The deposition is carried out by low pressure decomposition of silane at substantially 580° C. to cause a film of fine grained crystals of polysilicon to be formed having grain sizes averaging less than about 300 Angstroms after annealing. Such a film is very uniform and smooth, having a surface roughness less than about 100 Angstroms RMS. Annealing of the film and substrate at a low temperature results in a compressive strain in the field that decreases over the annealing time, annealing at high temperatures (e.g., over 1050° C.) yields substantially zero strain in the film, and annealing at intermediate temperatures (e.g., 650° C. to 950° C.) yields tensile strain at varying strain levels depending on the annealing temperature and time. Further processing of the polysilicon films and the substrate can yield isolated diaphragms of the polysilicon film which are supported only at edges by the substrate and which have substantial lateral dimensions, e.g., 1 cm by 1 cm. Such that structures can be used as pressure sensor diaphragms, X-ray masks, and optical filters, and can be provided with holes of varying sizes, shape and number, which can serve as X-ray mask patterns. The diaphragms can be provided with numerous holes of uniform size and spacing which allows the diaphragms to be used as filters in ultrafiltration applications.

Epitaxial growth of silicon: A molecular-dynamics simulation.

Abstract: We have studied the epitaxial growth of silicon using molecular-dynamics techniques. The model consists of a temperature-controlled Si(111) substrate, with the Si atoms projected towards the substrate as is done in the laboratory. The atoms interact via a potential developed by Stillinger and Weber to simulate the bulk properties of Si. We find that at low substrate temperatures the growth is not well ordered; this is in accordance with experimental observation. It is precisely the opposite of what occurs in spherically symmetric potentials that were used to simulate the growth of metallic films. At higher substrate temperatures the growth is into properly stacked, crystalline Si layers. In contrast to the growth of metals (spherically symmetric potentials), the atomic mobility on the growing surface and the thermal conductivity of the system are much lower for Si; the results of this simulation and those of our previous work are in agreement with experimental observations showing, as expected, that a major determining factor in epitaxial growth of films is the nature of the interaction potential.

Significant Efficiency Increase in Self‐Driven Photoelectrochemical Cell for Water Photoelectrolysis

Abstract: A theory relating the electrochemical and solid-state properties of semiconductors to their photoelectrochemical behavior has been used to predict the electrodes that, when combined, will give the optimum efficiencies for the splitting of water by means of solar light to hydrogen and oxygen. This paper represents the first application of this theory. A p-type indium phosphide electrode has been decorated with platinum and combined with an n-type gallium arsenide electrode which has been protected against photocorrosion by depositing a thin film of Mn-oxide on it. Examination has been made of the individual photoelectrochemical behavior of these electrodes in aqueous solution. The I-V curves of these electrodes indicated that, when placed together in a cell, they would spontaneously give rise to hydrogen and oxygen when photoirradiated. X-ray photoelectron spectroscopic examination of the protected gallium arsenide electrode showed no indication of the substrate, i.e., the Mn-oxide completely covered the gallium arsenide.

Novel microstructures for the in situ measurement of mechanical properties of thin films

Abstract: This paper discusses microfabricated structures designed for the in situ measurement of the mechanical properties of thin films under residual tensile stress. The film is deposited and patterned on a (100) silicon substrate in which 5‐μm‐thick diaphragms have been fabricated. When the silicon diaphragm is etched from the backside in an SF6 plasma, the microstructures are released and deform under the residual tension. Measurement of this deformation in conjunction with appropriate mechanical models determines the mechanical properties of interest. We have used these structures to study benzophenonetetracarboxylicdianhidride‐oxydianiline/metaphenylene‐diamine polyimide films. Typical value for the residual stress to modulus ratio in this case was determined to be 0.011±0.001 while the ultimate strain at break was found to be 4.5% for 5.5‐μm‐thick films. For thicker films (8.5 μm), the film did not fail until 8% strain was reached.

X-ray scattering studies of thin films and surfaces: thermal oxides on silicon

Abstract: A triple-axis X-ray spectrometer has been used to examine the reflectivity and surface scattering from silicon wafers with various thicknesses of oxide surface layers (from 10 to 100 AA). The X-ray techniques provide accurate information on the thickness of the surface oxide layer, the electron density of the roughness of both the surface interface and the substrate to layer interface. The use of a triple-axis spectrometer has two important advantages over the more conventional X-ray reflectivity techniques. It allows accurate reflectivity measurements to be carried out on samples which are, macroscopically, far from flat, such as semiconductor wafers in preparation for device fabrication. It also enables the intensity of the specularly reflected X-ray beam to be measured without contamination from the appreciable small-angle scattering which can occur from a microscopically rough surface. To illustrate this point, reflectivity measurements from a high-quality glass optical flat are also described.

Multilayer interconnection for integrated circuit structure having two or more conductive metal layers

Abstract: Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer which may be in contact with an underlying silicon substrate and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer of conductive metal such as an aluminum base metal; and an upper barrier layer which may be in contact with a second aluminum base metal layer and which is selected from the class consisting of TiW, TiN, MoSi x and TaSi where x equals 2 or more.

Field emission vacuum devices

Abstract: A vacuum valve device comprises a substrate on which is formed an updoped silicon layer from which a silicon dioxide layer is grown. First, second and third electrode structures are formed on the silicon dioxide layer by depositing a metallic layer and etching away unwanted portions of the layer. The first electrode structure has a pointed end and/or a sharp edge and/or is formed of low work function material so that, when a suitable voltage is applied between the first and third electrode structures, electrons are emitted from the first electrode structure due to a field emission process. Electrons therefore flow from the first to the third electrode structure substantially parallel to the substrate. The second electrode structure acts as a control electrode.

Superconducting Sn/Sn-oxide/Sn tunneling junctions as high-resolution x-ray detectors

Abstract: In a superconducting detector, the energy resolution is expected to be superior than in a semiconductor detector, owing to the thousand times smaller energy gap Δ. The performance of Sn/Sn‐oxide/Sn tunneling junctions (operated in the Giaever mode at T=0.32 K) exposed to 6‐keV x‐ray photons of a 55Fe source is presented. The best energy resolution observed is 67 eV (FWHM). Extrapolating to vanishing electronic noise, an intrinsic resolution of 0.7% (FWHM) is obtained. This is an order of magnitude worse than expected from the statistics of the 2.5×106 primary electron charges produced, and is believed to be due to geometrical effects in the films. The energy response of the detector is nonlinear, owing to the self‐recombination of the free charge carriers. At a fixed bias voltage, the pulses generated in either film of the junction were observed to have the same sign. If the junctions are evaporated onto a silicon substrate, most of the pulses originate, via phonon backscattering, from x‐ray photons inter...

Semiconductor device using copper metallization

Abstract: A semiconductor device comprises a silicon substrate, an insulating film in which a contact hole is formed, a metallic layer deposited on said silicon substrate through the contact hole, for forming an ohmic contact to the silicon substrate, a barrier layer deposited on the metallic layer, for preventing reaction and interdiffusion between copper and silicon, and a metallization film including at least copper deposited on the barrier layer.

Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

Abstract: The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.

Laser planarization of nonrefractory metal during integrated circuit fabrication

Abstract: Nonrefractory micrometer-thick deposited metal or metallization, for example, aluminum and aluminum alloy films, on integrated circuits are planarized by momentarily melting them with optical pulses from a laser, such as a xenon chloride excimer laser. The substrate, as well as any intervening dielectric and conducive layers, are preheated to preferably one-half the melting temperature of the metal to be planarized, thereby enhancing reflow of the metal upon melting. This improves planarization and reduces stress in the resolidified metal. Laser planarization offers an attractive technique for fabricating multilayer interconnect structures, particularly where a number of ground or power planes are included. Excellent step coverage and via filling is achieved without damaging lower layers of interconnect.

Deposition of Diamond-like Carbon Films by Pulsed-Laser Evaporation

Abstract: Diamond-like carbon thin films were deposited by pulsed-laser evaporation. A carbon target was irradiated by a Xe-Cl laser with a power density of 3×108 W/cm2. Ions were mixed with vaporized atoms. Deposition rates were typically 200 A/ min. Film properties changed with substrate temperature. The films deposited at 50°C were diamond-like, as confirmed by refractive index (2.1 to 2.2), optical transparenty and chemical resistance. Hydrogen-free films were produced. Optical band gap was 1.4 eV and electrical resistivity was 108 Ω-cm. No crystallinity was observed.

Field-effect transistor having a delta-doped ohmic contact

Abstract: A field-effect transistor is created on a GaAs semi-insulating substrate (e.g. 100) using molecular beam epitaxy by fabricating a delta-doped monolayer with a silicon dopant between two undoped GaAs layers grown over the semi-­insulating substrate. A plurality of delta-doped monolayers (e.g. 111, 112, 113, 114, 115) are grown over the surface of the upper undoped layer (e.g. 103) interleaved with layers of GaAs (e.g. 121, 122, 123, 124, 125) having a thickness equal to or less than the tunneling width of electrons in GaAs. A channel (e.g. 127) is etched through the plurality of delta-doped monolayers to permit a gate electrode (e.g. 131) to contact the upper undoped GaAs layer. Source and drain electrode (e.g. 132 and 133)s are deposited over the delta-doped monolayers on each side of the channel.

Semiconductor thin films

Abstract: An improved method and apparatus for optimizing the electrical properties while crystallizing material is disclosed. In this invention, a material which is to be crystallized is formed on a substrate and subjected to a heat treatment to intentionally induce thermal stress while crystallizing the material. The heat treatment melts the material being crystallized and when the material solidifies, a built-in stress is retained which, in the case of n-doped Si on fused silica results in a tensile stress which produces an electron mobility in the film of 870 cm 2 /volt-sec as compared to similarly fashioned unstressed n-doped Si on SiO 2 coated Si which has an electron mobility of 500 cm 2 /volt-sec.

Manufacture of semiconductor device

Abstract: PURPOSE:To realize a quality MESFET provided with a source, a gate, and a drain with the gaps between them constant and smaller and provided with a gate electrode enhanced in thickness by a method wherein a trench is provided in the surface of a semiconductor layer and, in the trench, a Schottky junction is formed between a gate electrode buried in the trench and the semiconductor layer for the construction of a MESFET. CONSTITUTION:On the semi-insulating GaAs substrate 11, an N-type layer 12 is epitaxially grown. Onto the entire surface of such a wafer, an AuGe layer and then an ohmic metal layer 13 are attached. Heat treatment is accomplished, which is followed by patterning whereby a 2.5mum gap is provided between a source and a drain. The ohmic metal layer 13 and the N-type layer 12 are then subjected to ion beam etching. A plasma SiO2 film 14 is provided and subjected to etching which is accomplished vertical to the substrate surface. Next, three layers of Ti, Pt, and Au are laid on the entire surface, in that order. Ion beam etching is accomplished at 30 deg. to the direction vertical to the substrate surface, after which Au and Pt are retained only at a gate section 15. Etching follows, after which Ti is retained only under the gate section 15 for the completion of a three-layer Schottky gate electrode.

Silicon surface cleaning by low dose argon‐ion bombardment for low‐temperature (750 °C) epitaxial silicon deposition. I. Process considerations

Abstract: A low‐energy argon sputter process has been optimized to successfully remove native oxide from a silicon surface at elevated temperatures without introducing permanent damage. The process relies upon confining all sputtering events to the near‐surface region of the silicon and exploits the enhancement of sputter efficiencies observed for silicon and silicon dioxide above 600 °C. The procedure has been implemented as an in situ etch for low‐temperature (below 800 °C), very low‐pressure (1–10 mTorr), epitaxial silicon deposition in a high vacuum ambient. The reactor and conditions employed are presented along with measures of residual substrate damage as a function of processing conditions, and the process limitations are discussed. A companion paper describes the excellent structural quality of the resultant epitaxial films. The ion energies (100 eV) and fluxes (5×1013 cm−2 s−1) employed represent a significant departure from conventional sputter cleaning processes.