Showing papers on "Substrate (electronics) published in 1992"

Methods of forming an interconnect on a semiconductor substrate

Abstract: A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

Atmospheric pressure chemical vapor deposition of gallium doped zinc oxide thin films from diethyl zinc, water, and triethyl gallium

Abstract: Gallium doped zinc oxide films have been deposited in the temperature range 150 to 470 °C from 0.05% diethyl zinc, 0.8% water, and various triethyl gallium concentrations. The films are polycrystalline with crystallite sizes varying between 275 and 500 A for undoped films and between 125 and 400 A for doped films. Only those films deposited above 430 °C are highly oriented and have their c axes perpendicular to the substrate plane. The electron density, conductivity, and mobility always increase with temperature. Thicker films have higher conductivity and mobility than thinner films. The refractive index is reduced from 1.96 to 1.73 when the electron density is increased from zero to 3.7×1020 cm−3. For films deposited at 370 °C with a gallium concentration of about 2.5 at. %, the ratio of conductivity to visible absorption coefficient increases from 0.03 to 1.25 Ω−1 when the film thickness increases from 0.11 to 1.2 μm. A film deposited at 470 °C with a gallium concentration of 2.4 at. % and a thickness o...

Method of producing semiconductor substrate

Abstract: A method of producing a semiconductor substrate, which comprises forming a monocrystalline silicon layer on a porous silicon substrate by epitaxial growth and applying an oxidation treatment to the porous silicon substrate and the monocrystalline silicon layer at least near the interface between the porous silicon substrate and the monocrystalline silicon layer.

Wide-gap semiconductor InGaN and InGaALN grown by MOVPE

Abstract: We have achieved InGaN growth on sapphire substrates at temperatures substantially higher than conventional growth temperatures for InGaN. When the growth temperature was changed from 500 (conventional) to 800° C (this work) in InGaN, the x-ray diffraction line width (full width at half maximum) decreased from 100 to 30 min. At 77 K, edge emission was observed in PL. In order to further improve crystalline quality, we have investigated ZnO as a lattice-matching substrate. First, the surface treatment and the resistance to the reducing atmosphere at high temperatures was briefly investigated. We report the first successful lattice-matched growth of InGaN. The x-ray diffraction line width of InGaN grown on ZnO was about 20% smaller than that of films grown on sapphire substrates, thus using lattice-matched substrates was shown to have an effect on improving the crystalline quality of InGaN. Single crystal InGaAlN has been also realized on sapphire substrates. The indium, gallium and aluminum contents were 2.2, 22.5 and 74.3%, respectively. The optical transmission characteristic of this InGaAlN was measured.

Bilayer metallization cap for photolithography

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO₂. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Off-axis laser deposition of YBa2Cu3O7-δ thin films

Abstract: We report on YBa2Cu3O7−δ thin‐film preparation by a new laser deposition geometry, the so‐called off‐axis laser deposition. Combined with radiation‐based substrate heating, this results in c‐axis oriented, epitaxial YBa2Cu3O7−δ thin films with critical current densities above 106 A/cm2 at 77 K and zero field and an exceptionally good surface quality, with complete absence of the otherwise observed laser droplets. As proved by atomic force microscopy, the surface roughness is <80 A over an area of at least 10×10 μm2. Using this off‐axis geometry it is possible to coat both sides of a substrate simultaneously, providing a one‐step process in double‐sided thin‐film deposition. Both YBa2Cu3O7−δ films on the substrate show identical superconducting properties.

Antireflection surfaces in silicon using binary optics technology

Abstract: Binary optics processing methods were applied to a silicon substrate to generate an array of small pillars in order to enhance transmission. The volume fraction of the silicon in the pillars was chosen to simulate a single homogeneous antireflection layer, and the pillar height was targeted to be a quarter-wave thickness. A mask was generated, using a graphics computer-aided design system; reactive-ion etching was used to generate the pillars. An improvement in long-wavelength infrared transmission is observed, with diffraction and scattering dominating at shorter wavelengths.

Chemical vapor deposition method for forming fluorine containing silicon oxide film

Abstract: A chemical vapor deposition method for forming a fluorine-containing silicon oxide film comprises introducing a gaseous mixture of alkoxysilane or its polymers as a source gas with fluoroalkoxysilane added thereto into a reaction chamber and performing decomposition of the gaseous mixture to deposit the fluorine-containing silicon oxide film onto a substrate. During the formation of the fluorine-containing silicon oxide film, at least one of compounds containing phosphorus or boron such as organic phosphorus compounds and organic boron compounds may be evaporated and introduced into said gaseous mixture, thereby adding at least one of phosphorus and boron to said fluorine-containing silicon oxide film. The fluorine-containing oxide film may be formed by effecting the decomposition of the gaseous mixture in the presence of ozone gas, or under ultraviolet radiation, or gas plasma.

Liquid crystal device

Abstract: PURPOSE:To provide the liquid crystal device for which a polymer dispersion type liquid crystal material is used and which has a large capacity, is bright and is increased in operating speed and to allow the easy and inexpensive production of this device by joining diodes provided in each of picture element electrodes in multiplex CONSTITUTION:This liquid crystal device 6 is constituted by crimping the dispersion liquid crystal material between an active matrix substrate 2 provided with the diodes 7 joined in multiplex to each of the picture element electrodes 1 and a signal electrode substrate 4 provided with signal electrodes 3 The active matrix substrate 2 provided with the diodes 7 for each of the picture element electrodes 1 and joined with the diodes 7 in multiplex refers to the substrate which is formed by laminating the diodes 7 in multiple layers on or alongside the respective fractioned picture element electrodes 1 consisting of ITO, SnO2, etc, on a substrate consisting of glass, etc, or laminating these diodes in multiple layers and connecting the diodes in series by lower electrodes 8 and metallic wirings 9 The respective diodes 7 provided in the adjacent picture element electrodes 1, the lower electrodes 8 and the metallic wirings 9 are insulated by insulating films 10

Modeling of agglomeration in polycrystalline thin films : application to TiSi2 on a silicon substrate

Abstract: An equilibrium model for agglomeration in polycrystalline thin films which considers the energy balance between the grain boundary energy and both surface and substrate interface energies is presented. It predicts that small grain size, low grain boundary energy, and high film surface and interface energies should promote resistance to agglomeration, and shows that the substrate‐film interface can play a significant role in the process. It also predicts a critical grain size limiting formation of a discontinuous island structure. This easily calculable value is significantly smaller than that found in previous modeling. The critical grain size, the importance of the substrate interface, and some of the assumptions are shown to be consistent with transmission microscope observations of TiSi2 thin films deposited on Si substrates.

Crystal compensated superconducting thin film formed of oxide superconductor material

Abstract: A superconducting thin film formed on a substrate, comprising at least one oxide superconductor layer formed on the principal surface of said substrate and at least one oxide layer formed of an oxide which compensates for crystalline incompleteness at the surface of said oxide superconductor layer, and which is arranged on or under the superconducting layer

A bulk silicon dissolved wafer process for microelectromechanical devices

Abstract: A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated without additional masking steps. It is also possible to fabricate elements with thickness-to-width aspect ratios in excess of 10:1. Measurements of various kinds of laterally driven comb structures processed in this manner, some of which are intended for application in a scanning thermal profilometer, are described. They comprise shuttle masses supported by beams that are 160-360 mu m long, 1-3 mu m wide, and 3-10 mu m thick. Some of the shuttles are mounted with probes that overhang the edge of the die by 250 mu m. Resonant frequencies from 18 to 100 kHz and peak-to-peak displacements up to 18 mu m have been measured. >

Manufacture of semiconductor substrate

Abstract: PURPOSE: To remarkably lessen the defects in the single crystalline layer on an insulator by sticking a second substrate onto the nonporous single crystalline semiconductor layer made on the porous layer of a first substrate, and then, separating these two substrate at the porous layer, and then, removing the second substrate and the porous layer on the first substrate CONSTITUTION: The surface layer of an Si single crystalline substrate 11 is made porous 12, and a nonporous single crystalline Si layer 13 is made hereon Next, another Si supporting substrate 14 and the single crystalline Si layer 13 are stuck fast to each other through an insulating layer 15 at high temperature, and then those are stuck together by anode junction, pressurization, or heat treatment, or these combination Next, the boards are separated at the porous Si layer 12 Furthermore, the porous Si layer 12 is removed selectively That is, the single crystallized Si layer 13 in film shape is left on the insulating substrate 15+14 by etching only the porous Si layer 12 by electroless wet chemical etching Alternatively, with the single crystalline Si layer 13 as a polishing stopper, the porous Si layer 12 is removed by selective polishing COPYRIGHT: (C)1995,JPO

Nitride based semiconductor device and manufacture thereof

Abstract: A nitride based semiconductor device, wherein provided are a substrate (23), a first layer comprising an oriented polycrystalline nitride based semiconductor (24, 29, 32, 35, 39, 45, 46, 49) which is formed directly on the substrate (23) and has a thickness less than 5000 angstrom, operation layers (25, 26, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 47, 48) made of single crystal nitride based semiconductors and formed directly on the first layer, and electrodes (27, 28, 43, 44) connected with predetermined places and at least one electrode (28, 44) of the electrodes (27, 28, 43, 44) are in connection with the first layer. The semiconductor device is manufactured by a crystal growth equipment by a molecular beam epitaxy method, wherein provided are a gas source (7) which feeds a compound containing nitrogen in the form of a gas, solid sources (2, 3, 4) which feed group III elements, and sources (5, 6) which feed n-type and p-type dopants. The first layer is created on the substrate (9) at a growth speed of 0.1-20 angstroms/sec by feeding the gas-like compound containing nitrogen and the group III elements onto the surface of the substrate (9) under the pressure less than 10⁻⁵ Torr and at a temperature of the substrate (9) of 300-1000 °C. The operation layer is created on the first layer at a growth speed of 0.1-10 angstroms/sec by feeding the gas-like compound containing nitrogen and the group III elements onto the surface of the first layer under the pressure less than 10⁻⁵ Torr and at the temperature of the substrate of 300-1000 °C.

High power, high frequency metal-semiconductor field-effect transistor formed in silicon carbide

Abstract: A high power, high frequency, metal-semiconductor field-effect transistor comprises a bulk single crystal silicon carbide substrate, an optional first epitaxial layer of p-type conductivity silicon carbide formed upon the substrate, and a second epitaxial layer of n-type conductivity silicon carbide formed upon the first epitaxial layer. The second epitaxial layer has two separate well regions therein that are respectively defined by higher carrier concentrations of n-type dopant ions than are present in the remainder of the second epitaxial layer. Ohmic contacts are positioned upon the wells for respectively defining one of the well regions as the source and the other as the drain. A Schottky metal contact is positioned upon a portion of the second epitaxial layer that is between the ohmic contacts and thereby between the source and drain for forming an active channel in the second epitaxial layer when a bias is applied to the Schottky contact.

Preparation of c-Axis Oriented AlN Thin Films by Low-Temperature Reactive Sputtering

Abstract: C-axis oriented aluminum nitride (AlN) thin films on (110) silicon were prepared by reactive RF magnetron sputtering in argon and nitrogen atmosphere without substrate heating. We investigated the dependence of some properties for the AlN thin film on sputtering conditions, especially N2 concentration. It was found that c-axis orientation tended to improve gradually with decreasing N2 concentration. The full width of half the maximum intensity (FWHM) of the rocking curve for a (002) plane of hexagonal AlN was 1~2 degrees at a 10% N2 concentration. This was a suitable value for surface acoustic wave (SAW) device. IDT/AlN/(110)Si structure SAW resonators were fabricated. It was confirmed that the insertion loss was 14 dB and phase velocity was 4800 m/s, respectively.

Non-contact optical techniques for measuring surface conditions

Abstract: Thermal, optical, physical and chemical characteristics of a substrate (11) surface are determined with non-contact optical techniques that include illuminating (23) the surface with radiation having a ripple intensity characteristic (51), and then measuring the combined intensities (53) of that radiation after modification by the substrate surface and radiation emitted from the surface. Precise determinations of emissivity, reflectivity, temperature, changing surface composition, the existence of any layer formed on the surface and its thickness are all possible from this measurement. They may be made in situ and substantially in real time, thus allowing the measurement to control (39, 41) various processes of treating a substrate surface. This has significant applicability to semiconductor wafer processing and metal processing.

Voltage variable capacitor.

Abstract: A voltage variable capacitor (10) has as the base substrate a silicon wafer with a layer of high resistivity semiconductor material on top of the substrate. An insulating layer (16) of a metal oxide having a dielectric constant greater than the dielectric constant of the semiconductors (12), such as zirconium titanate, is formed on top of the high resistivity layer, and a metal electrode (18) is formed on the insulating layer (16). When the electrode is energized, a depletion layer (20) is formed in the high resistivity layer. By varying the voltage applied to the electrode, the capacitance of the device is altered.

Crystallographically Aligned Ferroelectric Films Usable in Memories and Method of Crystallographically Aligning Perovskite Films

Abstract: A ferroelectric memory and its method of making in which a highly c-axis oriented layer (56) of ferroelectric lead zirconate titanate (PZT) is epitaxially deposited at between 640° and 710° C. upon a crystalline film (54) of yttrium barium copper oxide (YBCO), acting both as growth template and bottom electrode. A top electrode (58) is formed over the ferroelectric layer to complete the memory element. The two electrodes are preferably composed of the same perovskite conductor of the same cyrstalline orientation, most preferably, a-axis oriented YBCO. The structure can be grown on a silicon substrate (50) with an intermediate buffer layer (52) of yttria-stabilized zirconia. The ferroelectric behavior is optimized if the structure is cooled from its growth temperature at about 20° C./min. Such a-axis oriented perovskite thin films can be grown by continuously depositing the same or different perovskite material, but dividing the deposition into three temperature stages, a first at a temperature favoring a-axis oriented growth, a second gradually increasing the temperature to a temperature favoring c-axis growth, and a third at the c-axis growth temperature. Nonetheless, a high-quality a-axis oriented film is grown. The memory can be rejuvenated after it has become fatigued by applying a pulse of magnitude equal to that of the writing pulse but of considerably longer duration.

Pulsed gas plasma-enhanced chemical vapor deposition of silicon

Abstract: A substrate having silicon receptive surface areas is maintained in a plasma enhanced chemical vapor deposition (PECVD) chamber at a temperature, and under sufficient gas flow, pressure and applied energy conditions to form a gas plasma. The gas plasma is typically made up of hydrogen, but may be made up of mixtures of hydrogen with other gasses. A discontinuous flow of silane gas of predetermined duration and predetermined time spacing is introduced to produce at least one timed pulse of silane gas containing plasma, whereby a thin layer of silicon is deposited on the receptive areas of the substrate. The thin layer of silicon is exposed to the hydrogen gas plasma between the brief deposition time cycles and may result in the modification of the silicon layer by the hydrogen plasma. The surface modification may include at least one of etching, surface hydrogenation, surface bond reconstruction, bond strain relaxation, and crystallization, and serves the purpose of improving the silicon film for use in, for example, electronic devices. Repeated time pulses of silane gas and subsequent hydrogen plasma exposure cycles can result in selective deposition of silicon on predetermined receptive areas of a patterned substrate. Selective deposition of silicon can serve the purpose of simplifying electronic device manufacturing, such as, for example, the fabrication of amorphous silicon thin film transistors with low contact resistance in a single PECVD pump-down procedure.

Light emitting diode

Abstract: PURPOSE:To form an edge light-emitting LED element whose light-emitting output change by a temperature is small by a method wherein an active layer is formed at an acute angle to an electrode and light is taken out directly in a direction which is nearly parallel to the electrode. CONSTITUTION:An n-type GaAs buffer layer 2 is grown heteroepitaxially on a low-resistance n-type Si substrate 1 by a molecular beam epitaxy method or an organometallic vapor growth method. In addition, an n-type GaAlAs layer 3, a GaAs active layer 4 and a p-type GaAlAs layer 5 are epitaxially grown sequentially; after that, one part is etched and removed. After that, an ITO 6 as a transparent conductive substrate is formed by a sputtering operation. The substrate 1 and the ITO 6 are polished and tilted with reference to the active layer 4. Au electrodes 7 high in reflectivity are formed on the substrate 1 and the ITO 6 by a sputtering operation. Thereby, it is possible to form an edge light-emitting LED element whose light-emitting change by a temperature is small.

Ti/TiN/Ti contact metallization

Abstract: The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer. A metal layer including aluminum is then formed on top of the titanium layer or the titanium nitride layer to form the contact metallization with the doped silicon region in the semiconductor.

Substrate Temperature Dependence of Transparent Conducting Al-Doped ZnO Thin Films Prepared by Magnetron Sputtering

Abstract: A technique is demonstrated that improves the substrate spatial distributions of resistivity and film thickness of transparent conducting oxide thin films prepared using a conventional dc planar magnetron sputtering method. The spatial distributions of Al-doped ZnO (AZO) films are markedly improved by deposition onto substrates at temperatures above 300°C. Large-area AZO films with a resisitivity of 3-6×10-4 Ωcm can be produced at a substrate temperature of 350°C.

Dislocation Mechanisms of Relaxation in Strained Epitaxial Films

Abstract: Advances in the methods of deposition and characterization of crystalline films of submicron thickness have been dramatic over the past two decades. A principal motivation for development of this technology has been the potential for use of thin film semiconductor materials in electronic and optoelectronic devices. The main function of these devices is to control transport of electrons in a way which permits high spatial density, and in which the carriers are highly mobile, that is, they show fast response with little power consumption. Spatial control of mobile electrons can be facilitated by combining materials, forming a material heterostructure, with one or more of these materials being a thin film. Carrier confinement is enforced by a difference in energy band structure across the interface acting as a barrier. The exploitation of this physical effect in device design is called bandgap engineering. A great deal of attention has been focused on film/substrate systems involving the III-V compounds (InGaAs/GaAs, for example), as well as on II-VI compounds for optical applications (ZnSe/GaAs, for example). Current efforts are also directed toward SiGe/Si and GaAs/Si systems to exploit well-developed silicon device technology.

Impact ionization and positive charge formation in silicon dioxide films on silicon

Abstract: Positive charge formation and its possible relationship to impact ionization in silicon dioxide have been controversial issues for many years. In this study, band‐gap ionization due to the development of a high‐energy tail in the hot‐electron energy distribution is shown to occur in films thicker than 20.0 nm at fields higher than 7 MV/cm. This process is demonstrated to ‘‘directly’’ account for hole currents in the substrate circuit of n‐channel field‐effect transistors and for the observation of positively trapped charges accumulating at the substrate‐silicon/silicon‐dioxide interface at low injected‐carrier fluences (less than 0.001 C/cm2) before the onset of trap creation.

Base electrodes for high dielectric constant oxide materials in silicon technology

Abstract: Several conductive structures which appeared to be usable as base electrodes in VLSI capacitors based on high dielectric materials have been annealed in oxygen at 650 °C. The studied structures were Pt/TiN, Pt/Ta, Au/TiN, Ru, and RuO2/Ru, prepared under a variety of conditions. The structures have been studied by Rutherford backscattering (RBS) and Auger Electron Spectroscopy (AES). It was found that none of the pure metals, Pt, Au, or Ru, can prevent the diffusion of oxygen to the underlying layer and its oxidation, thus causing a possible break in the electrical conduction path to the silicon substrate. Of the investigated materials, in the thickness range ≤ 110 nm only the RuO2/Ru couple preserved its electrical connectivity to the Si substrate and prevented diffusion of silicon to the surface of the electrode.

Tungsten silicide (WSIX) deposition process for semiconductor manufacture

Abstract: A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with a silane source gas followed by deposition of the tungsten silicide film with a dichlorosilane source gas. This two step process allows dichlorosilane to be used as a silicon source gas for depositing a tungsten silicide film at a lower temperature than would otherwise by possible and without plasma enhancement. Tungsten silicide films deposited by this process are characterized by low impurities, good step coverage, and low stress with the silicon substrate.

Properties of indium tin oxide films prepared by the electron beam evaporation method in relation to characteristics of indium tin oxide/silicon oxide/silicon junction solar cells

Abstract: Indium tin oxide (ITO)/silicon oxide/silicon (Si) junction solar cells were produced by depositing ITO on a thin silicon oxide‐covered single‐crystal Si substrate using the electron‐beam evaporation method. The current‐voltage (I‐V) characteristics strongly depended on the incident angle (θi) of the evaporated ITO vapor to the Si substrate during the ITO deposition, as well as the post‐deposition heating temperature (Th) and the kind of the ambient gases during post‐deposition heat treatment. The ITO films deposited at θi=0° and treated at Th=380 °C in air formed a high‐energy barrier with p‐Si, and formed ohmic contact with n‐Si. X‐ray diffraction analysis showed that the ITO films deposited at θi=0° contained metal indium. The amount of the metal indium decreased either by reducing the deposition rate of the ITO film or by raising the substrate temperature during the ITO deposition. The ITO films deposited at θi=45° and treated at Th=350∼450 °C in hydrogen, on the other hand, formed a high‐energy barrie...

Use of palladium as an adhesion layer and as an electrode in ferroelectric memory devices

Abstract: A ferroelectric capacitor for a ferroelectric memory device includes a substrate (10), a silicon dioxide layer (20), a palladium adhesion layer (30), a bottom electrode (40) of platinum, a metal or an alloy, a ferroelectric material (50) and a top electrode (60) of platinum, a metal or an alloy.

Chemical Bath Deposition of CdS Thin Films: Electrochemical In Situ Kinetic Studies

Abstract: Chemical bath deposition of cadmium sulfide thin films from solutions has been studiedin situ using electrochemical open‐circuit potential change (EOCPC) measurements. An explanation of the EOCPC dependence with film thickness in terms of space‐charge region theory has been reported. The effect of various parameters on the growth and on the film quality is presented (temperature, concentration of reacting species, and film thickness). The structural and electrical properties of thin films prepared by this method have been studied. The x‐ray diffraction analysis shows evidence that the orientation perpendicular to the substrate surface is highly preferential confirming that the growth evolves from nucleation on the substrate. From resistivity and EOCPC measurements the following values of the electrical properties of the material have been obtained: dark conductivity about 10−7 (Ω cm)−1, photoconductivity about 10−2 (Ω cm)−1, carrier concentration about 10−13 cm−3, and carrier mobility about 2 cm2 V−1 s−1.