Showing papers on "Substrate (electronics) published in 1996"

Are Single Molecular Wires Conducting

Abstract: Molecular wire candidates inserted into “nonconducting” n -dodecanethiol self-assembled monolayers on Au{111} were probed by scanning tunneling microscopy (STM) and microwave frequency alternating current STM at high tunnel junction impedance (100 gigohms) to assess their electrical properties. The inserted conjugated molecules, which were 4,4′-di(phenylene-ethynylene)benzenethiolate derivatives, formed single molecular wires that extended from the Au{111} substrate to about 7 angstroms above and had very high conductivity as compared with that of the alkanethiolate.

Organic field‐effect transistors with high mobility based on copper phthalocyanine

Abstract: Organic field‐effect transistors that employ copper phthalocyanine (Cu–Pc) as the semiconducting layer can function as p‐channel accumulation‐mode devices. The charge carrier mobility of such devices is strongly dependent on the morphology of the semiconducting thin film. When the substrate temperature for deposition of Cu–Pc is 125 °C, a mobility of 0.02 cm2/V s and on/off ratio of 4×105 can be obtained. These features along with the highly stable chemical nature of Cu–Pc make it an attractive candidate for device applications.

Effect of strongly favorable substrate interactions on the thermal properties of ultrathin polymer films.

Abstract: The thermal behavior of ultrathin films of poly-(2)-vinylpyridine spin-cast on acid-cleaned silicon oxide substrates is considered. The interaction between the polymer and the substrate is polar in nature and very favorable. As a means of examining the thermal properties of the films, x-ray reflectivity is used to measure the temperature dependence of the film thickness. This experimentally measured thickness-temperature data is used to determine transition temperatures and thermal expansivities. Significantly increased transition temperatures (20-50 \ifmmode^\circ\else\textdegree\fi{}C above the measured bulk glass transition temperature) are observed in ultrathin polymer films. The transition temperature increases with decreasing film thickness, while the degree of thermal expansion below the transition temperature decreases with decreasing film thickness. If one assumes that a region of reduced chain mobility exists near the solid substrate-polymer interface, an analysis of the measured thermal expansion behavior below the transition temperature indicates that the length scale of substrate interactions is on the order of the macromolecular size.

Stress measurements in silicon devices through Raman spectroscopy: Bridging the gap between theory and experiment

Abstract: The different steps that have to be taken in order to derive information about local mechanical stress in silicon using micro‐Raman spectroscopy experiments, including theoretical and experimental aspects, are discussed. It is shown that the calculations are in general less complicated when they are done in the axes system of the sample. For that purpose, the secular equation is calculated in the axes system [110], [−110], [001], which is important for microelectronics structures. The theory relating Raman mode shift with stress tensor components is applied using two analytical stress models: uniaxial stress and planar stress. The results of these models are fitted to data from micro‐Raman spectroscopy experiments on Si3N4/poly‐Si lines on silicon substrate. In this fit procedure, the dimensions of the laser spot and its penetration depth in the substrate are also taken into account.

Formation and growth of black spots in organic light‐emitting diodes

Abstract: We report electroluminescence (EL) degradation studies of thin‐film organic light‐emitting diodes under ambient conditions. Bilayer organic ITO/TPD/Alq3/Mg/Ag devices were studied via EL and photoluminescence (PL) microscopy. In situ imaging of device luminescing areas and measurement of sample luminance were performed, allowing for a detailed study of black spot formation and luminance reduction under constant voltage stress conditions. Post‐stress devices were further characterized using PL microscopy, and it was found that black spots result from delamination of the metal at the Alq3/Mg interface initiated by pinholes on the cathode, caused by substrate defects.

Properties of carbon ion deposited tetrahedral amorphous carbon films as a function of ion energy

Abstract: Ion energy, controlled by the substrate bias, is an important parameter in determining properties of films deposited by the filtered cathodic vacuum arc technique. The substrate bias determines the ion energy distribution of the growth species. The ion energy is varied, while keeping the other deposition conditions constant, in order to study the effect of ion energy on the film properties. The films were characterized by their optical and mechanical parameters using an ellipsometer, surface profilometer, optical spectrometer, and nanoindenter. Electron energy‐loss spectroscopy and Raman spectroscopy were used for structural analysis of the films.

Method for forming shallow trench isolation

Abstract: A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resist layer that defines an active region on the sacrificial layer is applied. Thereafter, the portions of the sacrificial layer, the silicon nitride layer, the pad oxide layer and the substrate are removed to form a trench. Portions of the silicon nitride layer are undercut, and a dielectric layer is formed to fill the trench. The dielectric layer is planarized until the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed.

Hardness, elastic modulus, and structure of very hard carbon films produced by cathodic‐arc deposition with substrate pulse biasing

Abstract: The hardness, elastic modulus, and structure of several amorphous carbon films on silicon prepared by cathodic‐arc deposition with substrate pulse biasing have been examined using nanoindentation, energy loss spectroscopy (EELS), and cross‐sectional transmission electron microscopy. EELS analysis shows that the highest sp3 contents (85%) and densities (3.00 g/cm3) are achieved at incident ion energies of around 120 eV. The hardness and elastic modulus of the films with the highest sp3 contents are at least 59 and 400 GPa, respectively. These values are conservative lower estimates due to substrate influences on the nanoindentation measurements. The films are predominantly amorphous with a ∼20 nm surface layer which is structurally different and softer than the bulk.

Method of manufacturing a semiconductor device using a metal which promotes crystallization of silicon and substrate bonding

Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming a first insulating film on a first substrate; forming a second insulating film on the first insulating film; forming an amorphous silicon film on the second insulating film; holding a metal element that promotes the crystallization of silicon in contact with a surface of the amorphous silicon film; crystallizing the amorphous silicon film through a heat treatment to obtain a crystalline silicon film; forming a thin-film transistor using the crystalline silicon film; forming a sealing layer that seals the thin-film transistor; bonding a second substrate having a translucent property to the sealing layer; and removing the first insulating film to peel off the first substrate.

Gallium nitride-based III-V group compound semiconductor

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Memory cell incorporating a chalcogenide element and method of making same

Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Passivation of electroluminescent organic devices

Abstract: A passivated organic device including a transparent layer of conductive material formed on a supporting substrate. An active organic media formed on the transparent layer and an electrode formed on the active organic media, the electrode including a thin layer of lithium formed on the active organic media and a layer of indium overlying and passivating the layer of lithium, and completing the electrode.

Nucleation layer evolution in metal‐organic chemical vapor deposition grown GaN

Abstract: The structure and morphology of low growth temperature GaN nucleation layers have been studied using atomic force microscopy (AFM), reflection high energy electron diffraction (RHEED), and transmission electron microscopy (TEM). The nucleation layers were grown at 600 °C by atmospheric pressure metalorganic chemical vapor deposition (MOCVD) on c‐plane sapphire. The layers consist of predominantly cubic GaN (c‐GaN) with a high density of stacking faults and twins parallel to the film/substrate interface. The average grain size increases with increasing layer thickness and during the transition from low temperature (600 °C) to the high temperatures (1080 °C) necessary for the growth of device quality GaN. Upon heating to 1080 °C the nucleation layer partially converts to hexagonal GaN (h‐GaN) while retaining a high stacking fault density. The mixed cubic‐hexagonal character of the nucleation layer region is sustained after subsequent high‐temperature GaN growth.

Measurements of stress during vapor deposition of copper and silver thin films and multilayers

Abstract: Copper and silver single layer and multilayered thin films were thermal vapor deposited onto cantilevered substrates [Si(100) with native oxide] near room temperature in ultrahigh vacuum. The total force per unit width (F/w) in the film during and after deposition was determined from the change in substrate curvature measured in situ by a laser scanning technique. The intrinsic component of F/w was obtained by subtraction of the thermal component, which was obtained by measuring the product of the biaxial modulus of the film (Yf) and the difference in coefficients of thermal expansion of the substrate and the film (Δαs−f) while each sample was still in the ultra‐high vacuum deposition chamber. For all samples, the measured value of YfΔαs−f was substantially lower than the calculated value based on the {111} biaxial modulus and the coefficients of thermal expansion of the bulk materials, even though x‐ray diffraction indicated strong {111} film texture. During deposition, a general trend in F/w was found r...

Method of forming a fluorinated silicon oxide layer using plasma chemical vapor deposition

Abstract: A method of forming a fluorinated silicon oxide dielectric layer (33) by plasma chemical vapor deposition. The method includes the steps of creating a plasma in a plasma chamber (10) and introducing a silicon-containing gas, a fluorine-containing gas, oxygen and an inert gas such that the gases are excited by the plasma and react proximate a substrate (16) to form a fluorinated silicon oxide layer on the surface of the substrate (16). The fluorinated layer so formed has a dielectric constant which is less than that of a silicon oxide layer.

Influence of substrate‐induced biaxial compressive stress on the optical properties of thin GaN films

Abstract: The influence of biaxial stress on the optical properties of thin GaN films is studied by x‐ray diffraction and Raman and photoluminescence spectroscopy. The stress is caused by differences in the thermal expansion coefficient and lattice mismatch between the film and c‐plane sapphire substrates. In particular, the influence of various thicknesses of AlN buffer layers on the strain in GaN films is studied. GaN/AlN films were deposited by low pressure metal organic chemical vapor deposition using triethylgallium and tritertbutylaluminum and ammonia. We observe a pronounced reduction of strain in the GaN films with increasing buffer thickness: An AlN buffer layer thicker than 200 nm eliminates the stress completely. Estimates of the linear coefficient for the near band gap luminescence shift due to biaxial compressive strain yield a value of 24 meV/GPa.

Chemical vapor deposition reactor system and integrated circuit

Abstract: A method of and apparatus for depositing a silicon oxide layer onto a wafer or substrate is provided. The present method includes introducing into a processing chamber a process gas including silicon, oxygen, boron, phosphorus and germanium to form a germanium doped BPSG oxide layer having a reflow temperature of less than 800° C. Preferred embodiments of the present method are performed in either a subatmospheric CVD or a plasma enhanced CVD processing apparatus.

Hard elastic carbon thin films from linking of carbon nanoparticles

Abstract: HARD carbon thin films find many technological applications—as protective or biocompatible coatings, for instance. A very hard and elastic form of carbon nitride, in which curved graphene sheets are interlinked owing to the presence of small amounts of nitrogen, has recently been reported1. The hardness of these films is thought to arise from the presence of sp3-like bonds that introduce curvature into and bind together the sp2-bonded graphitic planes, rather as they do in hard, highly tetrahedrally bonded amorphous carbon films2–4. Here we show that hard, elastic thin films of pure carbon can be created by depositing closed, hollow graphitic carbon nanoparticles—nanotubes5 and carbon onions6—onto a substrate at high velocity. The particles are apparently disrupted on impact, causing them to link up. Electron-energy-loss spectra reveal a reduction in π (sp2) bonding in the intersecting regions of the nanoparticles, supporting the idea that they are covalently linked by tetrahedral sp3 bonds.

Semiconductor device having an MIS structure

Abstract: A semiconductor device including a GaAs semiconductor substrate, an insulating layer which is made of material selected from the group MgS, MgSSe and CaZnS and is formed on the GaAs substrate, and a conductive electrode formed on the insulating layer.

Apparatus for reducing process drift in inductive coupled plasma etching such as oxide layer

Abstract: A plasma processing chamber includes a substrate holder and a gas distribution plate having an inner surface facing the substrate holder, the inner surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The inner surface is cooled by adding a heat transfer gas such as helium to process gas supplied through the gas distribution plate. The chamber can include a dielectric window between an antenna and the gas distribution plate. The control of the temperature of the inner surface facing the substrate minimizes process drift and degradation of the quality of the processed substrates during sequential processing of the substrates such as during oxide etching of semiconductor wafers.

A critical thickness condition for a strained compliant substrate/epitaxial film system

Abstract: The physical system under study is a single crystal film grown epitaxially on a substrate of comparable thickness which is constrained to remain flat. In general, the layers are strained due to a mismatch in lattice parameter between the film and substrate materials. The free energy change of the system due to formation of strain‐relaxing interface misfit dislocations is estimated, and the discriminating case of zero energy change leads to a critical thickness condition on mismatch strain, film thickness, substrate thickness, and crystallographic slip orientation which is necessary for the spontaneous formation of such dislocations. The condition obtained generalizes the Matthews–Blakeslee (MB) criterion for a thin film on a thick substrate to the case of a complaint substrate/epitaxial film system, and it reduces to the MB criterion when either the film or substrate is relatively thick.

Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film

Abstract: A multilayer thin film of the invention has an oxide thin film formed on a semiconductor single crystal substrate, and the oxide thin film includes at least one epitaxial thin film composed mainly of zirconium oxide or zirconium oxide stabilized with a rare earth metal element (inclusive of scandium and yttrium). Included is an oriented thin film formed on the oxide thin film from a dielectric material of perovskite or tungsten bronze type with its c-plane unidirectionally oriented parallel to the substrate surface. Consequently, there are provided a perovskite oxide thin film of (001) orientation, a substrate for an electronic device comprising the thin film, and a method for preparing the thin film.

CoFe2O4 thin films grown on (100) MgO substrates using pulsed laser deposition

Abstract: Thin films (≊04 μm) of cobalt ferrite (CoFe2O4) have been grown on single‐crystal (100) MgO substrates using pulsed laser deposition (PLD) The phase, orientation, and microstructure of the as‐deposited films were investigated as a function of substrate temperature (ie, 200–800 °C) at a constant oxygen deposition pressure of 30 mTorr The as‐deposited films were found to be single phase, well oriented, and approximately matching the stoichiometry of the target, but the cubic lattice constant of the films depended on the substrate temperature indicating that the films were strained The greatest effect of the substrate temperature was on the magnetic properties of the as‐deposited films At 800 °C, 4πMs was measured to be 5370 G which is approximately the accepted bulk value for cobalt ferrite In addition, PLD cobalt ferrite films grown at substrate temperatures of 600 and 800 °C exhibited a uniaxial magnetic anisotropy with an easy direction normal to the film plane Films grown at 200 and 400 °C also

Chain End Effects and Dewetting in Thin Polymer Films

Abstract: The dewetting of thin films of end-functionalized polymers, ω- and α,ω-barium sulfonato polystyrenes, on a silicon substrate has been investigated as a function of initial film thickness, molecular...

Acrylate composite barrier coating process

Abstract: A thermoplastic container or packaging material is given low oxygen permeability by coating with a crosslinked acrylate layer and a layer of oxygen barrier material deposited over the acrylate layer. Another acrylate layer may be deposited over the oxygen barrier. The oxygen barrier is selected from the group consisting of silicon oxide, aluminum oxide and metal. The acrylate layer may be formed from a photopolymerizable polyfunctional acrylate that is sufficiently low viscosity to be sprayed on the substrate or applied by dipping. Alternatively, the acrylate layer is a polymerization product of an acrylate monomer which is evaporated in a vacuum, condensed on the substrate and polymerized by irradiation by ultraviolet or an electron beam. The surface of the thermoplastic substrate is prepared for deposition of the acrylate by either flame treating the surface of the substrate to heat it above its melting point without deforming the substrate to thereby smooth the surface, or by plasma treating the surface for enhancing adhesion of the acrylate. Chilling the substrate enhances deposition efficiency.

Production of substrate for tensilely strained semiconductor

Abstract: A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Method of fabricating an air-filled waveguide on a semiconductor body

Abstract: A method of using layers of gold metallization and a thick film coating of photo-sensitive material to form an air-filled microwave waveguide structure on the outer surface of a semiconductor body, such as a monolithic microwave integrated circuit commonly referred to as an MMIC, so that the waveguide can be coupled to the active and passive devices of the MMIC. First, a patterned metallization layer is formed on a substrate. A mold of a waveguide is fabricated by masking and then etching another metallization layer. The mold is turned over face down on the patterned metallization layer and bonded to the patterned metallization layer, Then, any unnecessary material is etched away.

Electron Trapping in Porphyrin-Sensitized Porous Nanocrystalline TiO2 Electrodes

Abstract: Electron trapping in electrochemical solar cells based on porous nanocrystalline TiO2 electrodes has been investigated. As light-absorbing dye, zinc 5,10,15,20-tetracarboxyphenylporphyrin is used. The spectral photocurrent response under front- and back-side irradiation reveals the existence of an active region, located near the transparent conducting substrate, where charge separation takes place. Due to electron trapping, this region increases when an additional white light bias is applied. In an indifferent electrolyte, the shape of the photocurrent action spectra depends on the applied potential. The contribution of the weaker absorbing Q bands is enhanced when negative potentials are applied. In this case the electron traps in the porous TiO2 film are filled. Their location in the bandgap is 0.5−0.6 eV below the conduction band edge. Consequently, electron trap filling enlarges the active region where charge separation takes place, which leads to an enhanced collection efficiency.

Si-Ge CMOS semiconductor device

Abstract: To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer 11 of Si 1−x Ge x inhibiting boron diffusion is provided between the strongly doped layer 10 and the intrinsic surface region 7 , for example with x=0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.