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Showing papers on "Substrate (electronics) published in 1999"


Patent
12 Jul 1999
TL;DR: In this paper, the oxide thin film formed on a substrate contains copper oxide and strontium oxide as a main component and exhibits p-type conductivity at a bandgap of at least 2 eV.
Abstract: An object of the invention is to provide an oxide thin film which exhibits a widegap or transparency and p-type conductivity although it has heretofore been very difficult to form. The oxide thin film formed on a substrate contains copper oxide and strontium oxide as a main component and exhibits p-type conductivity at a bandgap of at least 2 eV.

1,087 citations


Journal ArticleDOI
TL;DR: In this paper, ZnO thin films were epitaxially grown on c-sapphire substrates by pulsed laser deposition at substrate temperatures of 500-800 °C.
Abstract: ZnO thin films were epitaxially grown on c-sapphire substrates by pulsed laser deposition at substrate temperatures of 500–800 °C. The crystal structure of ZnO films follow the epitaxial relationship of (0001)ZnO∥(0001)Al2O3(1010)ZnO∥(1120)Al2O3. Both room temperature and cryogenic temperature photoluminescence showed a remarkable band-edge transition, and clear excitonic structures could be seen at cryogenic temperature. The optical refractive index was measured in the range of 375–900 nm by varying angle spectroscopic ellipsometry. The simulation was carried out using a Sellmeier equation.

545 citations


Journal ArticleDOI
TL;DR: A two-dimensional subwavelength structured (SWS) surface upon a crystal silicon substrate patterned by electron beam lithography and etched by an SF(6) fast atom beam was fabricated and the reflectivity was examined.
Abstract: We fabricated a two-dimensional subwavelength structured (SWS) surface upon a crystal silicon substrate. The SWS surface was patterned by electron beam lithography and etched by an SF(6) fast atom beam. The SWS grating had a conical profile, the period was 150 nm, and the groove was approximately 350 nm deep. The reflectivity was examined at 2002500-nm wavelengths. At 400 nm the reflectivity decreased to 0.5% from the 54.7% of the silicon substrate. We also used HeNe laser light to examine the reflectivity as a function of the incident angle.

426 citations


Patent
09 Jun 1999
TL;DR: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate This layer is much less likely to form a haze or bubbles in the layer, and is more likely to desorb water vapor during subsequent processing steps than other FSG layers as discussed by the authors.
Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers An undoped silicon glass (USG) liner protects the substrate from corrosive attack The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 08 μm with an aspect ratio of up to 45:1

331 citations


Patent
02 Jun 1999
TL;DR: In this article, a high electron mobility transistor (HEMT) is described that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate and an insulating gallium nitride layer on buffer layer, an active structure of aluminum gallium-nitride on the gallium oxide layer, a passivation layer on active structure, and respective source, drain, and gate contacts to the active structure.
Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.

322 citations


Journal ArticleDOI
TL;DR: In this paper, atomic layer growth of hafnium dioxide from HfCl4 and H2O has been studied at substrate temperatures ranging from 180-600°C.

310 citations


Journal ArticleDOI
TL;DR: InGaN multi-quantum-well structure laser diodes formed on the GaN layer above the SiO2 mask area can have a lifetime of more than 10,000 hours and the localized energy states caused by In composition fluctuation in the In GaN active layer are related to the high efficiency of the InGaN-based emitting devices.

280 citations


Journal ArticleDOI
TL;DR: In this paper, a bulk-quantity Si nanowires have been synthesized by thermal evaporation of a powder mixture of silicon and SiO2, and it was shown that at the initial nucleation stage, silicon monoxide vapor was generated from the powder mixture and condensed on the substrate.

274 citations


Journal ArticleDOI
Nuri W. Emanetoglu1, C. R. Gorla1, Y Liu1, S. Liang1, Yicheng Lu1 
TL;DR: In this paper, the epitaxial relationship between the ZnO films and the R-plane Al2O3 substrate was studied using X-ray diffraction techniques and an atomically sharp interface structure was revealed by high-resolution TEM.

255 citations


Journal ArticleDOI
TL;DR: In this paper, the mechanisms underlying selective etching of a SiO2 layer over a Si or Si3N4 underlayer, a process of vital importance to modern integrated circuit fabrication technology, has been studied.
Abstract: The mechanisms underlying selective etching of a SiO2 layer over a Si or Si3N4 underlayer, a process of vital importance to modern integrated circuit fabrication technology, has been studied. Selective etching of SiO2-to-Si3N4 in various inductively coupled fluorocarbon plasmas (CHF3, C2F6/C3F6, and C3F6/H2) was performed, and the results compared to selective SiO2-to-Si etching. A fluorocarbon film is present on the surfaces of all investigated substrate materials during steady state etching conditions. A general trend is that the substrate etch rate is inversely proportional to the thickness of this fluorocarbon film. Oxide substrates are covered with a thin fluorocarbon film (<1.5 nm) during steady-state etching and at sufficiently high self-bias voltages, the oxide etch rates are found to be roughly independent of the feedgas chemistry. The fluorocarbon film thicknesses on silicon, on the other hand, are strongly dependent on the feedgas chemistry and range from ∼2 to ∼7 nm in the investigated process...

244 citations


Patent
02 Dec 1999
TL;DR: An improved photovoltaic cell has an active silicon (Si) or silicon-germanium (SiGe) substrate subcell having an active upper side and characterized by a substrate bandgap as discussed by the authors.
Abstract: An improved photovoltaic cell has an active silicon (Si) or silicon-germanium (SiGe) substrate subcell having an active upper side and characterized by a substrate bandgap. One or more upper subcells are disposed adjacent the upper side and current matched with the substrate subcell, with the upper subcell(s) typically having bandgap(s) greater than the substrate bandgap. A transition layer may be placed intermediate the upper side and the upper subcell(s).

Patent
22 Jun 1999
TL;DR: In this article, a method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C.
Abstract: A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.

Patent
17 Nov 1999
TL;DR: In this paper, a gallium nitride microelectronic layer is fabricated by converting a surface of a (111) silicon layer to 3C-silicon carbide, then epitaxially grown on the converted surface of the silicon layer.
Abstract: A gallium nitride microelectronic layer is fabricated by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer. In one embodiment, the silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide. In another embodiment, the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate. In yet another embodiment, the (111) silicon layer is a portion of a Silicon-On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate. Lateral growth of the layer of 2H-gallium nitride may be performed by Epitaxial Lateral Overgrowth (ELO) wherein a mask is formed on the layer of 2H-gallium nitride, the mask including at least one opening that exposes the layer of 2H-gallium nitride. The layer of 2H-gallium nitride then is laterally grown through the at least one opening and onto the mask. A second, offset mask also may be formed on the laterally grown layer of 2H-gallium nitride and a second laterally grown layer of 2H-gallium nitride may be overgrown onto the offset mask. Lateral growth of the layer of 2H-gallium nitride also may be performed using pendeoepitaxial techniques wherein at least one trench and/or post is formed in a layer of 2H-gallium nitride to define at least one sidewall therein. The layer of 2H-gallium nitride is then laterally grown from the at least one sidewall. Pendeoepitaxial lateral growth preferably continues until the laterally grown sidewalls coalesce on the top of the posts or trenches. The top of the posts and/or the trench floors may be masked to promote lateral growth and reduce nucleation and vertical growth.

Journal ArticleDOI
TL;DR: In this article, the performances of thin-film poly-Si solar cells with a thickness of less than 5μm on a glass substrate have been investigated, where the active i-type polySi layer was fabricated by plasma chemical vapor deposition (CVD) at low temperature.
Abstract: The performances of thin-film poly-Si solar cells with a thickness of less than 5 μm on a glass substrate have been investigated. The cell of glass/back reflector/n-i-p type Si/ITO is well characterized by the structure of naturally surface texture and enhanced absorption with a back reflector (STAR), where the active i-type poly-Si layer was fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%), an open-circuit voltage of 0.539 V and a short-current density of 25.8 mA/cm2 as independently confirmed by Japan Quality Assurance. No light-induced degradation is observed. The optical and transport properties of poly-Si cells are summarized.

Journal ArticleDOI
TL;DR: In this article, a silicon carbide (SiC) nanowires on a silicon substrate were prepared using hot-filament-assisted chemical-vapor deposition with a solid silicon and carbon source.
Abstract: Silicon carbide (SiC) nanowires on a silicon substrate were prepared using hot-filament-assisted chemical-vapor deposition with a solid silicon and carbon source. The SiC nanowires show good field-emitting properties as revealed by the current–voltage characteristics. Together with its ease of preparation, these SiC nanowires are shown to have great potential in the area of electron field-emitting devices.

Patent
13 Aug 1999
TL;DR: In this article, a memory cell incorporating a chalcogenide element and a method of making same is disclosed, where a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells.
Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Journal ArticleDOI
TL;DR: The matrix assisted pulsed laser evaporation (MAPLE) as mentioned in this paper technique has been successfully used to deposit highly uniform thin films of a variety of organic materials including a number of polymers.

Journal ArticleDOI
TL;DR: In this article, a transparent polycrystalline p-n heterojunctions on a glass substrate were fabricated and the structure of the diode was n+-ZnO electrode/n- ZnO/p-SrCu2O2/In2−xSnxO3 electrode on the substrate.
Abstract: All oxide-based, transparent polycrystalline p–n heterojunctions on a glass substrate were fabricated. The structure of the diode was n+-ZnO electrode/n-ZnO/p-SrCu2O2/In2−xSnxO3 electrode on the substrate. The contact between the n- and p-type semiconducting oxides was found to be rectifying. The ratio of forward current to the reverse current exceeded 80 within the range of applied voltages of −1.5 to +1.5 V and the estimated diode factor (n value) was 1.62. The diode structure was fabricated on a glass plate with the total thickness of 1.3 μm and possessed an optical transmission of 70%–80% in the visible region.

Patent
08 Jun 1999
TL;DR: In this article, a process is provided for the formation of a thin film of gate dielectric or similar material on a silicon semiconductor substrate from an organic precursor by atomic layer epitaxy, wherein the organic precursor is introduced to react with the treated surface to form a bonded monolayer of reactive species.
Abstract: A process is provided for the formation of a thin film of gate dielectric or similar material on a silicon semiconductor substrate from an organic precursor by atomic layer epitaxy, wherein the organic precursor is introduced to react with the treated surface to form a bonded monolayer of reactive species. A second reactant is introduced to react with the surface to form the desired dielectric. After each step in the cycle, the reaction chamber is purged with an inert gas to prevent reactions except on the surface. The cycle is repeated tens to hundreds of times to achieve a desired final film thickness. No less frequently than every third cycle, the film undergoes a discrete treatment step wherein ozone is introduced into the chamber to oxidize carbon contaminants therein to form volatile products which are removed from the reaction chamber by purging with the inert gas. In a preferred embodiment where the substrate is silicon or polysilicon, a sub-monolayer of a protection material is formed by boding to silicon sites on the surface before the deposition of dielectric is begun. A preferred dielectric is gate aluminum oxide that is deposited using trimethyl aluminum as a precursor.

Patent
Egi Yuichiro1
04 Oct 1999
TL;DR: In this paper, a local interconnection layer comprised of a silicide film is formed the region of the amorphous silicon film portion lying in the interconnection formation portion and the regions of the single-crystalline silicon film portions.
Abstract: In a method of manufacturing a semiconductor device, gate electrodes are formed on a surface of a silicon substrate, and, over the surface of the silicon substrate thus formed, an amorphous silicon film is formed by deposition. Next, the amorphous silicon film is selectively grown to form single-crystalline film portions. Then, a resist is formed only on an interconnection formation portion. Thereafter, the amorphous silicon film portions and other than the amorphous silicon film portion which lies in the interconnection formation portion are removed. Then, a local interconnection layer comprised of a silicide film is formed the region of the amorphous silicon film portion lying in the interconnection formation portion and the regions of the single-crystalline silicon film portions. According to the above-mentioned manufacturing method, the step of forming the local interconnection layer is simplified which step was complicated in case of the conventional technique.

Patent
21 Jun 1999
TL;DR: In this paper, a transparent substrate particularly of glass, provided with a stack of thin layers having at least one metallic layer having properties in the infrared range particularly having low emissivity and two coatings having a base of dielectric material located one under and the other over the layer, as well as a protective metallic layer (5) place immediately over an in contact with the layer having property in the IR range, characterized in that in order to prevent the modification of properties of the stack, particularly optical and thermal properties, in the case where the substrate is submitted to a
Abstract: A transparent substrate particularly of glass, provided with a stack of thin layers having at least one metallic layer (4) having properties in the infrared range particularly having low emissivity and two coatings having a base of dielectric material located one (8) under and the other (9) over the layer having properties in the infrared range, as well as a protective metallic layer (5) place immediately over an in contact with the layer having properties in the infrared range, characterized in that in order to prevent the modification of properties of the stack, particularly optical and thermal properties, in the case where the substrate is submitted to a thermal treatment of the tempering or bending kind, firstly the second coating (9) having a base of dielectric material, includes a barrier layer for the diffusion of oxygen chosen from the following materials: components of silicon SiO2, SiOxCy, SiONNy, nitrates such as Si3N4 or AlN, carbides such as SiC, TiC, CrC, TaC of a thickness of at least 10 nanometers and preferably of at least 20 nanometers, and secondly the layer having properties in the infrared range is directly in contact with the underlying dielectric coating.

Journal ArticleDOI
TL;DR: In this article, a single crystal GaN thin film was successfully grown on a Si (111) substrate by means of atmospheric pressure metalorganic chemical vapor deposition (MOCVD) and the fullwidth at half maximum (FWHM) of the double-crystal X-ray rocking curve for GaN(0004) was 600 arcsec.
Abstract: A single crystal GaN thin film was successfully grown on a Si (111) substrate by means of atmospheric pressure metalorganic chemical vapor deposition. Though there is a large difference in thermal expansion coefficients between GaN and Si, an intermediate layer consisting of AlN and AlGaN improved the quality of GaN on Si and reduced meltback etching during growth. Pits and cracks were not observed on the substrate and a mirror-like surface was obtained. The full-width at half maximum (FWHM) of the double-crystal X-ray rocking curve for GaN(0004) was 600 arcsec. Photoluminescence measurement at room temperature for a Si-doped film revealed a sharp band-edge emission with a FWHM of 62.5 meV, which is the narrowest value reported to date.

Journal ArticleDOI
TL;DR: In this article, the cleanliness of indium tin oxide (ITO) sub-strates used in organic light-emitting diodes (OLEDs) is in- vestigated by contact angle measurement and by X-ray pho- toemission spectroscopy (XPS).
Abstract: The cleanliness of indium tin oxide (ITO) sub- strates used in organic light-emitting diodes (OLEDs) is in- vestigated by contact angle measurement and by X-ray pho- toemission spectroscopy (XPS). It was found that ultraviolet (UV) ozone treatment is quite effective in removing organic contamination on the ITO surface. The degree of surface con- tamination was checked by changes in contact angles and by XPS. Strong correlation can be established between these two techniques. OLEDs fabricated from UV-irradiated ITO sub- strates exhibit low turn-on voltage and superior brightness. There are now widespread interests in using organic or poly- meric fluorescent thin films for fabricating electroluminescent (EL) devices (1, 2). The basic structure of an organic EL de- vice consists of one or more layers of organic fluorescent materials sandwiched between an anode and a metal cathode. In most cases, a thin film of indium tin oxide (ITO), with a thickness in the order of 0:1 mm, is used as the anode ma- terial. The ITO layer can be prepared by standard sputtering techniques onto a glass plate or a plastic substrate. Since ITO is a transparent conductor, it also functions as the viewing side for the EL device. Although there are now numerous re- ports on EL devices fabricated by many different materials, few reports have been devoted to the preparation of ITO for EL devices. Since organic EL devices are thin film devices, a small amount of contamination on the surface of the an- ode can severely alter the work function, or the interfacial barrier height between the organic layer and the anode. Un- less the anode is thoroughly cleaned, the electrical and optical characteristics can be highly unstable and unpredictable. It is, therefore, of utmost importance that the ITO substrate is carefully cleaned before deposition of the organic layers. A variety of methods (3-8) have been developed in the preparation of ITO surfaces for organic light-emitting diodes (OLEDs). A summary of these methods is shown in Table 1.

Patent
23 Feb 1999
TL;DR: In this paper, an apparatus in which plasma is generated in the reactor and active species (radicals) are formed and film deposition is carried out on the substrate with this active species and precursor gas in which a partitioning plate 15 in which plurality of holes 22 has been formed is established.
Abstract: To suppress the formation of dust particles, prevent the implantation of ions into a substrate and to achieve a good plasma distribution in the vicinity of the substrate when depositing a silicon oxide film using TEOS, for example, by means of CVD on a substrate which has a large surface area, an apparatus in which plasma is generated in the reactor 12 and active species (radicals) are formed and film deposition is carried out on the substrate 11 with this active species and precursor gas in which a partitioning plate 15 in which a plurality of holes 22 has been formed is established. The reactor is divided into a plasma generating space 16 and a film deposition process space 17, in which the precursor gas is delivered directly into the film deposition process space 17 through a plurality of pathways which is established dispersed over and passing through the plasma generating space and the partitioning plate, and the active species which are formed in the plasma generating space are delivered into the film deposition process space through the plurality of holes which are established in the partitioning plate.

Journal ArticleDOI
09 Apr 1999-Science
TL;DR: Single-crystal films of the high-temperature cubic polymorph of bismuth oxide were epitaxially electrodeposited from an aqueous solution onto single-crystals gold substrates to provide a method for producing other nonequilibrium phases that cannot be accessed by traditional thermal processing.
Abstract: Single-crystal films are essential for devices because the intrinsic properties of the material, rather than its grain boundaries, can be exploited. Cubic bismuth oxide has the highest known oxide ion mobility, which makes it useful for fuel cells and sensors, but it is normally only stable from 729° to 825°C. The material has not been previously observed at room temperature. Single-crystal films of the high-temperature cubic polymorph of bismuth oxide were epitaxially electrodeposited from an aqueous solution onto single-crystal gold substrates. The 35.4 percent lattice mismatch was accommodated by forming coincidence lattices in which the bismuth oxide film was rotated in relation to the gold substrate. These results provide a method for producing other nonequilibrium phases that cannot be accessed by traditional thermal processing.

Journal ArticleDOI
Ma Jin1, Ji Feng1, Zhang De-heng1, Ma Hong-Lei1, Li Shu-ying1 
TL;DR: In this paper, the structural, optical and electrical properties of the zinc oxide films have been studied and the effects of heat treatment for the as-deposited films in air and vacuum are investigated.

Patent
21 Oct 1999
TL;DR: In this paper, a method and apparatus for depositing nano-porous low dielectric constant films by reaction of a silicon hydride containing compound or mixture optionally having thermally labile organic groups with a peroxide compound on the surface of a substrate.
Abstract: A method and apparatus for depositing nano-porous low dielectric constant films by reaction of a silicon hydride containing compound or mixture optionally having thermally labile organic groups with a peroxide compound on the surface of a substrate. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a foam structure. The nano-porous silicon oxide based films are useful for filling gaps between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures. Preferred nano-porous silicon oxide based films are produced by reaction of 1,3,5-trisilanacyclohexane, bis(formyloxysilano)methane, or bis(glyoxylylsilano)methane and hydrogen peroxide followed by a cure/anneal that includes a gradual increase in temperature.

Patent
Qing Ma1, Harry Fujimoto1
11 Jan 1999
TL;DR: An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate may have a via as mentioned in this paper, which is a solder bump that is attached to both the integrated circuit and the silicon subtstrate.
Abstract: An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon subtstrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

Patent
David Mui1, Dragan Podlesnik1, Wei Liu1, Gene Lee1, Nam-Hun Kim1, Jeff Chinn1 
10 Aug 1999
TL;DR: In this article, the authors proposed a method for rounding the bottom corners of a bottom trench using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.
Abstract: The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

Patent
17 Aug 1999
TL;DR: In this article, a method for forming an insulation layer over a substrate is described, which is particularly suitable for deposition of low dielectric constant films, where k is less than or equal to 3.0.
Abstract: A method for forming an insulation layer over a substrate. The method forms a carbon-doped silicon oxide layer by thermal chemical vapor deposition using an organosilane. The carbon-doped silicon oxide layer is subsequently cured and densified. In one embodiment, the cured film is densified in a nitrogen-containing plasma. The method is particularly suitable for deposition of low dielectric constant films, i.e., where k is less than or equal to 3.0. Low-k, carbon-doped silicon oxide methylsilane or di-, tri-, tetra-, or phenylmethylsilane. and ozone. The above method can be carried out in a substrate processing system having a process chamber; a substrate holder, a heater, a gas delivery system, and a power supply, all of which are coupled to a controller. The controller contains a memory having a computer-readable medium with a program embodied for directing operation of the system in accordance with above method.