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Showing papers on "Substrate (electronics) published in 2008"


Patent
10 Apr 2008
TL;DR: In this paper, a method of manufacturing a thin-film transistor (TFT) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first pattern group, forming an amorphous silicon layer and an oxide semiconductor layer, and forming a protection layer including a contact hole on the second pattern group.
Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

1,036 citations


Patent
14 Mar 2008
TL;DR: In this paper, a thin-film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate is described.
Abstract: Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the semiconductor layer is composed of P-type ZnO:N layers through a reaction of a mono-nitrogen gas with a zinc precursor, and the ZnO:N layer includes an un-reacted impurity element at a content of 3 at % or less.

1,032 citations


Journal ArticleDOI
TL;DR: In this article, the effect of substrate on the atomic/electronic structures of monolayer graphene is investigated and it is shown that the Raman features are independent of the substrate used.
Abstract: Graphene has attracted a lot of interest for fundamental studies as well as for potential applications. Till now, micromechanical cleavage (MC) of graphite has been used to produce high-quality graphene sheets on different substrates. Clear understanding of the substrate effect is important for the potential device fabrication of graphene. Here we report the results of the Raman studies of micromechanically cleaved monolayer graphene on standard SiO2 (300 nm)/Si, single crystal quartz, Si, glass, polydimethylsiloxane (PDMS), and NiFe. Our data suggests that the Raman features of monolayer graphene are independent of the substrate used; in other words, the effect of substrate on the atomic/electronic structures of graphene is negligible for graphene made by MC. On the other hand, epitaxial monolayer graphene (EMG) on SiC substrate is also investigated. Significant blueshift of Raman bands is observed, which is attributed to the interaction of the graphene sheet with the substrate, resulting in the change o...

700 citations


Journal ArticleDOI
TL;DR: In this article, a facile fabricating method has been established for large-area uniform silicon nanowires arrays, which were obtained by single crystals and epitaxial on the substrate.
Abstract: A facile fabricating method has been established for large-area uniform silicon nanowires arrays All silicon nanowires obtained were single crystals and epitaxial on the substrate Six kinds of silicon wafers with different types, surface orientations, and doping levels were utilized as starting materials With the catalysis of silver nanoparticles, room-temperature mild chemical etching was conducted in aqueous solution of hydrofluoric acid (HF) and hydrogen peroxide (H2O2) The corresponding silicon nanowires arrays with different morphologies were obtained The silicon nanowires possess the same type and same doping level of the starting wafer All nanowires on the substrate have the same orientation For instance, both (100)- and (111)-oriented p-type wafers produced silicon nanowires in the (100) direction For every kind of silicon wafer, the effect of etching conditions, such as components of etchant, temperature, and time, were systemically investigated This is an appropriate method to produce a

527 citations


Journal ArticleDOI
TL;DR: In this paper, the surface oxide layer on Cu nanoparticles synthesized in ambient atmosphere was minimized by adjusting the molecular weight of poly(N-vinylpyrrolidone) capping molecules, as confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses.
Abstract: With the aim of preparing a high performance conductive ink, we sought to control the surface chemistry of Cu nanoparticles so as to minimize surface oxidation. Specifically, the surface oxide layer on Cu nanoparticles synthesized in ambient atmosphere was minimized by adjusting the molecular weight of poly(N-vinylpyrrolidone) capping molecules, as confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses. In addition, we demonstrate that by minimizing the thickness of the surface oxide layer, Cu granular films with good conductivity could be obtained by sintering nanoparticle assembles. Finally, we fabricated highly conductive Cu patterns on a plastic substrate by ink-jet printing.

463 citations


Journal ArticleDOI
TL;DR: Large-area high density silicon nanowire arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate.
Abstract: Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 10 wires/cm 2 were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.

321 citations


Journal ArticleDOI
TL;DR: Fuel cell performance of the corrugated electrolyte membranes released from silicon substrate showed an increase of power density relative to membranes with planar electrolytes.
Abstract: A low temperature micro solid oxide fuel cell with corrugated electrolyte membrane was developed and tested. To increase the electrochemically active surface area, yttria-stabilized zirconia membranes with thickness of 70 nm were deposited onto prepatterned silicon substrates. Fuel cell performance of the corrugated electrolyte membranes released from silicon substrate showed an increase of power density relative to membranes with planar electrolytes. Maximum power densities of the corrugated fuel cells of 677 mW/cm2 and 861 mW/cm2 were obtained at 400 and 450 °C, respectively.

319 citations


Journal ArticleDOI
TL;DR: In this paper, the status and prospects for further development of reduced or indium-free transparent conducting oxide (TCO) materials for use in practical thin-film transparent electrode applications such as liquid crystal displays are presented.

307 citations


Patent
02 May 2008
TL;DR: In this paper, a method of removing at least a portion of a silicon oxide material is described, which is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus.
Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.

302 citations


Journal ArticleDOI
TL;DR: In this paper, a GaAs nanowire was synthesized by using a beam epitaxy Ga-assisted synthesis of GaAs wafer, and the nucleation and growth were seen to be related to the presence of a SiO2 layer previously deposited on the wafer.
Abstract: Molecular beam epitaxy Ga-assisted synthesis of GaAs nanowires is demonstrated. The nucleation and growth are seen to be related to the presence of a SiO2 layer previously deposited on the GaAs wafer. The interaction of the reactive gallium with the SiO2 pinholes induces the formation of nanocraters, found to be the key for the nucleation of the nanowires. With SiO2 thicknesses up to 30nm, nanocraters reach the underlying substrate, resulting into a preferential growth orientation of the nanowires. Possibly related to the formation of nanocraters, we observe an incubation period of 258s before the nanowires growth is initiated.

296 citations


Journal ArticleDOI
TL;DR: In this paper, a six-layer graded-refractive index (GRIN) AR coating made entirely of a single material, indium tin oxide (ITO), chosen for its high conductivity, high optical transmittance, and low contact resistance with GaN was presented.
Abstract: tion (AR) coatings, [7–10] and optical resonators. [11] In many cases, however, the unavailability of materials with desired refractive indices, particularly materials with very low refractive indices, prevents the implementation of optical components with very high performance. In addition, the choice of a material with desired refractive index often forces a compromise in other materials properties such as optical transmittance and electrical conductivity that are also important for most optoelectronic applications. Here, we show that oblique-angle deposition can be used to tailor the refractive index of a thinfilm material that is chosen for its desired material properties other than refractive index. The unique ability to control the refractive index of thin film materials allows one to eliminate Fresnel reflection, one of the fundamental limitations in lightextraction efficiency of light-emitting diodes (LEDs), by fabricating coatings whose refractive index gradually decreases from the refractive index of the active semiconductor layer to the refractive index of the surrounding medium. As an example of this concept, we present a six-layer graded-refractiveindex (GRIN) AR coating made entirely of a single material, indium tin oxide (ITO), chosen for its high conductivity, high optical transmittance, and low contact resistance with GaN. Each layer has a refractive index that is individually tuned to form a stack with refractive index graded from its dense ITO value down to the value close to that of air for an optimum AR performance. It is shown that GaInN LEDs with a GRIN ITOAR contact achieve a light-extraction efficiency enhancement of 24.3 % compared to the LEDs with dense ITO coating due to a strongly reduced Fresnel reflection at the ITO– air interface. Oblique-angle deposition is a method of growing porous thin films, and hence thin films with low-refractive index (lown), enabled by surface diffusion and self-shadowing effects during the deposition process. [12–16] In oblique-angle deposition, a random growth fluctuation on the substrate produces a shadow region that the incident vapor flux cannot reach, and a non-shadow region where incident flux deposits preferentially, thereby creating an oriented rodlike structure with high porosity. Figure 1 shows the cross-sectional scanning-electron microscopy (SEM) image of low-n ITO, which is electrically conductive and optically transparent in visible wavelengths, COMMUNICATION

Journal ArticleDOI
TL;DR: Large-area slantingly-aligned silicon nanowire arrays (SA-SiNW arrays) on Si(111) substrate have been fabricated by wet chemical etching with dry metal deposition method and employed in the fabrication of solar cells for the first time.
Abstract: Large-area slantingly-aligned silicon nanowire arrays (SA-SiNW arrays) on Si(111) substrate have been fabricated by wet chemical etching with dry metal deposition method and employed in the fabrication of solar cells for the first time. The formation of SA-SiNW arrays possibly results from the anisotropic etching of silicon by silver catalysts. Superior to the previous cells fabricated with vertically-aligned silicon nanowire arrays (VA-SiNW arrays), the SA-SiNW array solar cells exhibit a highest power conversion efficiency of 11.37%. The improved device performance is attributed to the integration of the excellent anti-reflection property of the arrays and the better electrical contact of the cell as a result of the special slantingly-aligned structure. The high surface recombination velocity of minority carriers in SiNW arrays is still the main limitation on cell performance.

Patent
Cheng-Hung Chang1, Yu-Rung Hsu1, Chen-Yi Lee1, Shih-Ting Hung1, Chen-Nan Yeh1, Chen-Hua Yu1 
05 Dec 2008
TL;DR: In this paper, a method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk Silicon substrate.
Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Journal ArticleDOI
TL;DR: Vertical light emitting diodes based on GaAs/InGaP core/shell nanowires, epitaxially grown on GaP and Si substrates, have been fabricated, enabling applications such as on-chip optical communication.
Abstract: Vertical light emitting diodes (LEDs) based on GaAs/InGaP core/shell nanowires, epitaxially grown on GaP and Si substrates, have been fabricated. The devices can be fabricated over large areas and can be precisely positioned on the substrates, by the use of standard lithography techniques, enabling applications such as on-chip optical communication. LED functionality was established on both kinds of substrate, and the devices were evaluated in terms of temperature-dependent photoluminescence and electroluminescence.

Journal ArticleDOI
TL;DR: This low band gap, asymmetric linear acene contains electron-withdrawing fluorine atoms, which lower the molecular orbital energies, allowing the injection of electrons in a high performance, ambipolar organic field-effect transistor composed of a single material.
Abstract: We present a high performance, ambipolar organic field-effect transistor composed of a single material. Ambipolar molecules are rare, and they can enable low-power complementary-like circuits. This low band gap, asymmetric linear acene contains electron-withdrawing fluorine atoms, which lower the molecular orbital energies, allowing the injection of electrons. While hole and electron mobilities of up to 0.071 and 0.37 cm2/V·s, respectively, are reported on devices measured in nitrogen, hole mobilities of up to 0.12 cm2/V·s were found in ambient, with electron transport quenched. These devices were fabricated on octadecyltrimethoxysilane-treated surfaces at a substrate temperature of 60 °C.

Patent
23 May 2008
TL;DR: In this paper, a method for manufacturing a photoelectric conversion device using a solar cell was proposed, in which a plurality of single crystal semiconductor substrates in each of which a damaged layer is formed at a predetermined depth is arranged over a supporting substrate having an insulating surface.
Abstract: A photoelectric conversion device which is excellent in photoelectric conversion characteristics is provided by effectively utilizing silicon semiconductor materials. The present invention relates to a method for manufacturing a photoelectric conversion device using a solar cell, in which a plurality of single crystal semiconductor substrates in each of which a damaged layer is formed at a predetermined depth is arranged over a supporting substrate having an insulating surface; a surface layer part of the single crystal semiconductor substrate is separated thinly using the damaged layer as a boundary so as to form a single crystal semiconductor layer over one surface of the supporting substrate; and the single crystal semiconductor layer is irradiated with a laser beam from a surface side which is exposed by separation of the single crystal semiconductor layer to planarize the surface of the single crystal semiconductor layer.

Journal ArticleDOI
TL;DR: In this article, the authors investigated magnetic and structural properties at the surface of epitaxial Ni2MnGa(110) Heusler films using x-ray absorption spectroscopy and magnetic circular dichroism both in transmission and total electron yield mode.
Abstract: We investigated magnetic and structural properties at the surface of epitaxial Ni2MnGa(110) Heusler films using x-ray absorption spectroscopy and x-ray magnetic circular dichroism both in transmission and total electron yield mode. The magnetic shape memory films were prepared by dc sputtering from a stoichiometric target onto sapphire substrates at an optimized substrate temperature of 773K. X-ray diffraction confirms a (110) oriented growth on Al2O3(112¯0) and an austenite to martensite transition at 270–280K. At the surface the martensitic phase transition and the magnetization are strongly suppressed. The deviation in the surface properties is caused by a Mn deficiency near the surface.

Patent
31 Mar 2008
TL;DR: In this paper, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer over an inter-poly dielectric stack disposed over a silicon oxide layer, and a control gate poly silicon layer over the second aluminum oxide layer.
Abstract: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

Patent
18 Sep 2008
TL;DR: In this paper, a method of forming a silicon-containing film was proposed, which consists of providing a substrate in a reaction chamber, injecting into the reaction chamber at least one silicon containing compound, and injecting into a co-reactant in the gaseous form at a temperature equal to or less than 550°C.
Abstract: A method of forming a silicon-containing film comprising providing a substrate in a reaction chamber, injecting into the reaction chamber at least one silicon-containing compound; injecting into the reaction chamber at least one co-reactant in the gaseous form; and reacting the substrate, silicon-containing compound, and co-reactant in the gaseous form at a temperature equal to or less than 550°C to obtain a silicon-containing film deposited onto the substrate. A method of preparing a silicon nitride film comprising introducing a silicon wafer to a reaction chamber; introducing a silicon-containing compound to the reaction chamber; purging the reaction chamber with an inert gas; and introducing a nitrogen-containing co-reactant in gaseous form to the reaction chamber under conditions suitable for the formation of a monomolecular layer of a silicon nitride film on the silicon wafer.

Journal ArticleDOI
TL;DR: It is demonstrated that semiconductor nanoribbons, in this case, a thin sheet of silicon on an oxidized silicon substrate, can approach the same sensitivity extending below the picomolar concentration regime in the biotin/streptavidin case.
Abstract: Direct electrical detection of biomolecules at high sensitivity has recently been demonstrated using semiconductor nanowires. Here we demonstrate that semiconductor nanoribbons, in this case, a thin sheet of silicon on an oxidized silicon substrate, can approach the same sensitivity extending below the picomolar concentration regime in the biotin/streptavidin case. This corresponds to less than ∼20 analyte molecules bound to receptors on the nanoribbon surface. The micrometer-size lateral dimensions of the nanoribbon enable optical lithography to be used, resulting in a simple and high-yield fabrication process. Electrical characterization of the nanoribbons is complemented by computer simulations showing enhanced sensitivity for thin ribbons. Finally, we demonstrate that the device can be operated both in inversion as well as in accumulation mode and the measured differences in detection sensitivity are explained in terms of the distance between the channel and the receptor coated surface with respect to...

Journal ArticleDOI
TL;DR: In this article, a map of formed microstructures is compiled as a function of back ground pressure and substrate temperature, and the conditions to obtain dense or porous films for YSZ and CGO are estab- lished.
Abstract: Yttrium-stabilized zirconia (YSZ) and cerium gadolinium oxide (CGO) thin films were prepared by pulsed laser deposition (PLD) under different ambient pressures and substrate temperatures. The microstructures of the obtained films are compared with existing structural zone models for thin-film growth. The model developed by Thornton (1974) for metallic sputtered films is applied to the metal oxide films grown by PLD and gives a good description for the growth process and the dependence of the microstructure on deposition temperature and pressure. A map of formed microstructures is compiled as a function of back- ground pressure and substrate temperature, and the conditions to obtain dense or porous films for YSZ and CGO are estab- lished. The two materials show the same dependence on temperature and pressure. Higher background pressure yields more porous films and a fully dense structure cannot be achieved for substrate temperatures in the range from room temperature to 800°C. Of special interest for us was the realization and characterization of dense films processed at low temperature (< 500°C) for the preparation of free-standing membranes to be used in a micro solid oxide fuel cell. We could achieve such films by pro- cessing at 400°C in 0.026 mbar of oxygen. In-plane electric conductivities of the films were measured and correlated with the microstructures.

Journal ArticleDOI
TL;DR: In this paper, the authors used bacterial cellulose (BC) membranes produced by gram-negative, acetic acid bacteria (Gluconacetobacter xylinus) as flexible substrates for the fabrication of organic light-emitting Diodes (OLED).

Journal ArticleDOI
TL;DR: In this paper, the structural and electrical performances of microcrystalline silicon (μc-Si:H) single junction solar cells co-deposited on a series of substrates having different surface morphologies varying from V-shaped to U-shaped valleys, are analyzed Transmission electron microscopy (TEM) is used to quantify the density of cracks within the cells.
Abstract: In the present paper, the structural and electrical performances of microcrystalline silicon (μc-Si:H) single junction solar cells co-deposited on a series of substrates having different surface morphologies varying from V-shaped to U-shaped valleys, are analyzed Transmission electron microscopy (TEM) is used to quantify the density of cracks within the cells deposited on the various substrates Standard 1 sun, variable illumination measurements (VIM) and Dark J(V) measurements are performed to evaluate the electrical performances of the devices A marked increase of the reverse saturation current density (J0) is observed for increasing crack densities By introducing a novel equivalent circuit taking into account such cracks as non-linear shunts, the authors are able to relate the magnitude of the decrease of Voc and FF to the increasing density of cracks © 2007 Elsevier BV All rights reserved

Patent
19 Dec 2008
TL;DR: In this article, methods for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD are described, by using disilane compounds as the silicon source, good deposition rates and uniformity are obtained.
Abstract: Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and uniformity are obtained.

Patent
13 Jun 2008
TL;DR: In this paper, a dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer is formed above a buffer layer having a lattice constant similar to a InP.
Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Journal ArticleDOI
TL;DR: Using the concept of sacrificial layers and elevation of Au catalyst modulated by growth condition, this work demonstrates for the first time a large area direct transfer process for nanowires formed by a bottom-up approach that can maintain both the position and alignment.
Abstract: We report the controlled growth of planar GaAs semiconductor nanowires on (100) GaAs substrates using atmospheric pressure metalorganic chemical vapor deposition with Au as catalyst. These nanowires with uniform diameters are self-aligned in direction in the plane of (100). The dependence of planar nanowire morphology and growth rate as a function of growth temperature provides insights into the growth mechanism and identified an ideal growth window of 470 ( 10 °C for the formation of such planar geometry. Transmission electron microscopy images reveal clear epitaxial relationship with the substrate along the nanowire axial direction, and the reduction of twinning defect density by about 3 orders of magnitude compared to III-V semiconductor nanowires. In addition, using the concept of sacrificial layers and elevation of Au catalyst modulated by growth condition, we demonstrate for the first time a large area direct transfer process for nanowires formed by a bottom-up approach that can maintain both the position and alignment. The planar geometry and extremely low level of crystal imperfection along with the transferability could potentially lead to highly integrated III-V nanoelectronic and nanophotonic devices on silicon and flexible substrates.

Patent
17 Oct 2008
TL;DR: In this paper, a method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process.
Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.

Journal ArticleDOI
TL;DR: In this article, the structural properties of spray-deposition ZnO:Cu thin films have been investigated by X-ray diffraction techniques and the results showed that polycrystalline structures are polycrystaline with hexagonal structure and show a good c-axis orientation perpendicular to the substrate.

Patent
Xinliang Lu1, Haichun Yang1, Zhenbin Ge1, Nan Lu1, David T. Or1, Chien-Teh Kao1, Mei Chang1 
07 Oct 2008
TL;DR: In this article, the authors provided methods for etching dielectric layers comprising of silicon and nitrogen, which may include providing a substrate having a dielectrically-compensated substrate, and forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma.
Abstract: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.

Patent
18 Dec 2008
TL;DR: In this article, the authors proposed a method of depositing low wet etch rate silicon nitride films on substrates using high-density plasma chemical vapor deposition techniques at substrate temperatures below 600° C.
Abstract: The present invention pertains to methods of depositing low wet etch rate silicon nitride films on substrates using high-density plasma chemical vapor deposition techniques at substrate temperatures below 600° C. The method additionally involves the maintenance of a relatively high ratio of nitrogen to silicon in the plasma and a low process pressure.