Showing papers on "Substrate (electronics) published in 2009"

Influence of Feature Size, Film Thickness, and Silicon Doping on the Performance of Nanostructured Hematite Photoanodes for Solar Water Splitting

Abstract: Photoanodes consisting of nanostructured hematite prepared by atmospheric pressure chemical vapor deposition (APCVD) have previously set a benchmark for solar water splitting. Here, we fully investigate this promising system by varying critical synthetic parameters and probing the photoanode performance to determine the major factors that influence operation. By varying the film thickness, we show film growth to be linear with an incubation time. We find no concern with electron transport for films up to 600 nm, but a higher recombination rate of photogenerated carriers in the hematite near the interface with the fluorine-doped tin oxide, as compared to the bulk section of the film. The mechanism for the formation of the thin film’s nanoporous dendritic structure is discussed on the basis of the results from varying the substrate growth temperate. The observed feature sizes of the film are found to depend strongly on this temperature and the presence of silicon dopant precursor (TEOS). Raman and Mossbauer...

Flexible full color organic light-emitting diode display on polyimide plastic substrate driven by amorphous indium gallium zinc oxide thin-film transistors

Abstract: We have fabricated 6.5 in. flexible full-color top-emission active matrix organic light-emitting diode display on a polyimide (PI) substrate driven amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). The a-IGZO TFTs exhibited field-effect mobility (μFE) of 15.1 cm2/V s, subthreshold slope of 0.25 V/dec, threshold voltage (VTH) of 0.9 V. The electrical characteristics of TFTs on PI substrate, including a bias-stress instability after 1 h long gate bias at 15 V, were indistinguishable from those on glass substrate and showed high degree of spatial uniformity. TFT samples on 10 μm thick PI substrate withstood bending down to R=3 mm under tension and compression without any performance degradation.

Large area few-layer graphene/graphite films as transparent thin conducting electrodes

Abstract: By dissolving carbon atoms decomposed from methane in a metal substrate at high temperatures, large area uniform few-layer graphene (FLG)/graphite films were precipitated on metal surfaces upon cooling. The thickness could be controlled by varying the amount of carbon atoms in the metal. Such films were transferred to glass slides after dissolving the metal substrate in an aqueous solution of Fe(NO3)3. Sheet resistances as low as 200 Ω/◻ with a transmittance of 85% were obtained from FLG films. The resistance and transmittance can be changed over one order of magnitude, making such films potentially useful for transparent thin conducting electrodes.

Method for manufacturing SOI substrate

Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.

Thin-film transistor

Abstract: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.

Synthesis, Transfer, and Devices of Single- and Few-Layer Graphene by Chemical Vapor Deposition

Abstract: The advance of graphene-based nanoelectronics has been hampered due to the difficulty in producing single- or few-layer graphene over large areas. We report a simple, scalable, and cost-efficient method to prepare graphene using methane-based CVD on nickel films deposited over complete Si/SiO2 wafers. By using highly diluted methane, single- and few-layer graphene were obtained, as confirmed by micro-Raman spectroscopy. In addition, a transfer technique has been applied to transfer the graphene film to target substrates via nickel etching. FETs based on the graphene films transferred to Si/SiO2 substrates revealed a weak p-type gate dependence, while transferring of the graphene films to glass substrate allowed its characterization as transparent conductive films, exhibiting transmittance of 80% in the visible wavelength range.

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Abstract: Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of silicon (~2.5 times10-6/degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Method of fabrication of a FinFET element

Abstract: The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element includes forming silicon fins on a substrate and selectively growing an epitaxial layer including germanium on the silicon fins. A Ge-condensation process may then be used to selectively oxidize the silicon of the Si-fin and transform the Si-fin to a Ge-fin. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates, and CMOS-compatible processes to form the Ge-FinFET element.

Semiconductor device and manufacturing method thereof

Abstract: A semiconductor device includes: a silicon substrate; and a field effect transistor including a gate insulating film over the silicon substrate, a gate electrode on the gate insulating film, and source and drain regions. The gate electrode includes, in part in contact with the gate insulating film, a crystallized Ni silicide region containing an impurity element of a conductivity type opposite to a conductivity type of a channel region in the field effect transistor.

Very High Mobility in Solution-Processed Organic Thin-Film Transistors of Highly Ordered [1]Benzothieno[3,2-b]benzothiophene Derivatives

Abstract: Field-effect mobility as high as 5 cm2/(V s) is achieved in solution-processed organic thin-film transistors with the development of a method for growing highly-oriented crystalline films of [1]benzothieno[3,2-b]benzothiophene derivatives. A droplet of the solution is sustained at an edge of a structure on an inclined substrate, so that the crystalline domain grows in the direction of inclination. The oriented growth realizes excellent molecular ordering that manifests itself in micrometer-scale molecular terraces on the surface as a result of the self-organizing function of the material. The unprecedented performance achieved using an easy fabrication process has increased attractiveness of organic thin-film transistors for industrial applications.

Method of Forming Conformal Dielectric Film Having Si-N Bonds by PECVD

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Vapor deposition method for ternary compounds

Abstract: Embodiments provide a method for depositing or forming titanium aluminum nitride materials during a vapor deposition process, such as atomic layer deposition (ALD) or plasma-enhanced ALD (PE-ALD). In some embodiments, a titanium aluminum nitride material is formed by sequentially exposing a substrate to a titanium precursor and a nitrogen plasma to form a titanium nitride layer, exposing the titanium nitride layer to a plasma treatment process, and exposing the titanium nitride layer to an aluminum precursor while depositing an aluminum layer thereon. The process may be repeated multiple times to deposit a plurality of titanium nitride and aluminum layers. Subsequently, the substrate may be annealed to form the titanium aluminum nitride material from the plurality of layers. In other embodiments, the titanium aluminum nitride material may be formed by sequentially exposing the substrate to the nitrogen plasma and a deposition gas which contains the titanium and aluminum precursors.

Substrate-dependent interface composition and charge transport in films for organic photovoltaics

Abstract: The buried interface composition of polymer-fullerene blends is found by near-edge x-ray absorption fine structure spectroscopy to depend on the surface energy of the substrate upon which they are cast. The interface composition determines the type of charge transport measured with thin film transistors. These results have implications for organic photovoltaics device design and the use of transistors to evaluate bulk mobility in blends.

Continuous Alloy-Composition Spatial Grading and Superbroad Wavelength-Tunable Nanowire Lasers on a Single Chip

Abstract: By controlling local substrate temperature in a chemical vapor deposition system, we have successfully achieved spatial composition grading covering the complete composition range of ternary alloy CdSSe nanowires on a single substrate of 1.2 cm in length. Spatial photoluminescence scan along the substrate length shows peak wavelength changes continuously from ∼500 to ∼700 nm. Furthermore, we show that under strong optical pumping, every spot along the substrate length displays lasing behavior. Thus our nanowire chip provides a spatially continuously tunable laser with a superbroad wavelength tuning range, unmatched by any other available semiconductor-based technology.

High-pressure Raman spectroscopy of graphene

Abstract: In situ high-pressure Raman spectroscopy is used to study monolayer, bilayer, and few-layer graphene samples supported on silicon in a diamond anvil cell to 3.5 GPa. The results show that monolayer graphene adheres to the silicon substrate under compressive stress. A clear trend in this behavior as a function of graphene sample thickness is observed. We also study unsupported graphene samples in a diamond anvil cell to 8 GPa and show that the properties of graphene under compression are intrinsically similar to graphite. Our results demonstrate the differing effects of uniaxial and biaxial strain on the electronic band structure.

Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature

Abstract: A method of depositing a silicon oxide film on a resist pattern or etched lines formed on a substrate by plasma enhanced atomic layer deposition (PEALD) includes: providing a substrate on which a resist pattern or etched lines are formed in a PEALD reactor; controlling a temperature of a susceptor on which the substrate is placed at less than 50° C. as a deposition temperature; introducing a silicon-containing precursor and an oxygen-supplying reactant to the PEALD reactor and applying RF power therein in a cycle, while the deposition temperature is controlled substantially or nearly at a constant temperature of less than 50° C., thereby depositing a silicon oxide atomic layer on the resist pattern or etched lines; and repeating the cycle multiple times substantially or nearly at the constant temperature to deposit a silicon oxide atomic film on the resist pattern or etched lines.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred etching directions.

Abstract: The metal-assisted etching direction of Si(110) substrates was found to be dependent upon the morphology of the deposited metal catalyst. The etching direction of a Si(110) substrate was found to be one of the two crystallographically preferred 100 directions in the case of isolated metal particles or a small area metal mesh with nanoholes. In contrast, the etching proceeded in the vertical [110] direction, when the lateral size of the catalytic metal mesh was sufficiently large. Therefore, the direction of etching and the resulting nanostructures obtained by metal-assisted etching can be easily controlled by an appropriate choice of the morphology of the deposited metal catalyst. On the basis of this finding, a generic method was developed for the fabrication of wafer-scale vertically aligned arrays of epitaxial [110] Si nanowires on a Si(110) substrate. The method utilized a thin metal film with an extended array of pores as an etching catalyst based on an ultrathin porous anodic alumina mask, while a prepatterning of the substrate prior to the metal depostion is not necessary. The diameter of Si nanowires can be easily controlled by a combination of the pore diameter of the porous alumina film and varying the thickness of the deposited metal film.

Stress management for tensile films

Abstract: The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate temperature causes less cracking in the dielectric film than flowable films formed in accordance with methods in the prior art. A compressive liner layer deposited prior to the formation of the gap-filling silicon oxide layer is described and reduces the tendency for the subsequently deposited film to crack. A compressive capping layer deposited after a flowable silicon-containing layer has also been determined to reduce cracking. Compressive liner layers and compressive capping layers can be used alone or in combination to reduce and often eliminate cracking. Compressive capping layers in disclosed embodiments have additionally been determined to enable an underlying layer of silicon nitride to be transformed into a silicon oxide layer.

One-step hydrothermal crystallization of a layered double hydroxide/alumina bilayer film on aluminum and its corrosion resistance properties.

Abstract: A zinc-aluminum layered double hydroxide (ZnAl-LDH)/alumina bilayer film has been fabricated on an aluminum substrate by a one-step hydrothermal crystallization method. The LDH film was uniform and compact. XRD patterns and SEM images showed that the LDH film was highly oriented with the c-axis of the crystallites parallel to the substrate surface. The alumina layer existing between the LDH film and the substrate was formed prior to the LDH during the crystallization process. Polarization measurements showed that the bilayer film exhibited a low corrosion current density value of 10(-8) A/cm(2), which means that the LDH/alumina bilayer film can effectively protect aluminum from corrosion. Electrochemical impedance spectroscopy (EIS) showed that the impedance of the bilayer was 16 MOmega, meaning that the film served as a passive layer with a high charge transfer resistance. The adhesion between the film and the substrate was very strong which enhances its potential for practical application.

Oxide etch with NH4-NF3 chemistry

Abstract: The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first gas and a second gas, and a ratio of the first gas and a second gas is determined by the desired removal rate.

Method of forming highly conformal amorphous carbon layer

Abstract: A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate,

Half integer quantum Hall effect in high mobility single layer epitaxial graphene

Abstract: The quantum Hall effect, with a Berry’s phase of π is demonstrated here on a single graphene layer grown on the C-face of 4H silicon carbide. The mobility is ∼20 000 cm2/V⋅s at 4 K and 15 000 cm2/V⋅s at 300 K despite contamination and substrate steps. This is comparable to the best exfoliated graphene flakes on SiO2 and an order of magnitude larger than Si-face epitaxial graphene monolayers. These and other properties indicate that C-face epitaxial graphene is a viable platform for graphene-based electronics.