Showing papers on "Subthreshold conduction published in 1978"

A charge-sheet model of the MOSFET

Abstract: Intuition, device evolution, and even efficient computation require simple MOSFET (metal-oxide-semiconductor field-effect transistor) models. Among these simple models are charge-sheet models which compress the inversion layer into a conducting plane of zero thickness. It is the purpose of this paper to test one such charge sheet model to see whether this approximation is too severe. This particular model includes diffusion which is expected to be important in the subthreshold and saturation regions. As a test the charge sheet model is applied to long-channel devices. Long-channel MOSFET behavior has been thoroughly studied, and is very well explained by the Pao-Sah double-integral formula for the current. Hence, a clear-cut test is a comparison of the charge sheet model with the Pao-Sah model. We find the charge sheet model has two advantages over the Pao-Sah model. (1) It leads to a very simple algebraic formula for the current of long-channel devices. The same formula applies in all regimes from subthreshold to saturation. Neither splicing nor parameter changes are needed. No discontinuities occur in either the current or the small-signal parameters, or in the derivatives of the small-signal parameters. (2) It is simpler to extend the charge sheet model to two or three dimensions than the Pao-Sah model. This simplification is a result of dropping the details of the inversion layer charge distribution. An important aspect of the gradual channel approximation is brought out by the analysis. Suppose the boundary condition relating the quasi-fermi level at the drain, φfL, to that at the source, φfo, namely φ ƒL =φ ƒ0 +V D where VD is the drain voltage, is applied in all bias regimes. Then it is shown that this means the potential at the drain end of the channel, φsL is not related to the potential at the source end of the channel, φso, by φ sL =φ s0 +V D Instead, φsL is computed, not imposed as a boundary condition. It is suggested that this failure of the potential to satisfy the boundary condition at the drain is justifiable. That is, φsL should be reinterpreted as the potential at the point in the channel where the gradual channel approximation fails. Hence, (2) may be relaxed. However, the “channel length” in the gradual-channel approximation now becomes a fitting parameter and is not the metallurgical source-to-drain separation. In addition several aspects of the long-channel MOSFET are brought out: (1) Pinch-off is achieved only asymptotically as the drain voltage tends to infinity. This is in marked contrast to the often-stated, textbook view that pinch-off is achieved for some finite drain voltage, the saturation voltage. (2) The channel or drain conductance approaches zero only asymptotically. (3) The transconductance saturates only asymptotically. Figures comparing the simple charge-sheet model formulas with the usual textbook formulas are included for direct-current vs drain voltage, channel conductance vs drain voltage, and transconductance vs drain voltage. The charge-sheet model agrees with the original Pao-Sah double-integral formula for the current at all gate and drain voltages, and possesses the correct subthreshold behavior. The textbook formulas do not.

Subthreshold conduction in MOSFET's

Abstract: The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.

Method for fabricating transistor structures having very short effective channels

Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.

Shot noise behaviour of subthreshold MOS transistors

Abstract: It is shown that assuming weak inversion, low drain current asymptotic value of the gate equivalent noise resistor is given by n2/2 UT/ID, corresponding to shot noise. Measurements confirming this theory as well as flicker noise measurements on n and p channel transistors integrated with either bulk or SOS CMOS silicon gate technology are presented.

BiMOS micropower ICs

Abstract: Design techniques suitable for micropower integrated circuits are discussed. Some systems require subpicoampere input bias and amplifier, timing, and logic functions with a several hundred milliampere output capability-at a standby current level of a few microamperes. MOSFETs are characterized well into their subthreshold regions and, in concert with standard bipolar devices, are shown to extend the performance capabilities of linear circuit portions. Applications of subthreshold circuits are very broad, however, because the high transconductance-to-current ratios of MOSFET pairs also provide order-of-magnitude improvements in offset temperature-drift and life stability. In combination with bootstrapped input protective networks, subthreshold BiMOS devices can provide operational-amplifier performance normally attained by only die-trimming techniques or hybrid construction. It is shown that the MOSFET is useful not only for its high-impedance input, but also in intermediate and output functions of linear/digital ICs.

The subthreshold behavior of SOS MOST's

Abstract: MOST subthreshold behavior is of importance in many modern dynamic and very-low-power circuits. SOS MOST's exhibit quite generally a lower transconductance than bulk Si MOST's. Comparison between SOS and bulk Si MOST's is made on the basis of a simple model in the weak inversion region. Experiments with n-and p-channel SOS MOST's fabricated with epi Si layer thicknesses ranging from 0.1 to 3 µm confirm the predicted decrease of transconductance in weak inversion with decreasing thickness. Quantitative agreement between model and experience is obtained if a ∼350-A thick nonconductive Si layer near the Si-sapphire interface is assumed. A transconductance jump observed for epi Si thickness equal to the surface maximum depletion width has not yet been explained. Further experiments including fabrication process, back-gate voltage measurements, and device dimensions were performed in order to investigate the low-transconductance origin. It is concluded that the only relevant parameters are the epi Si layer thickness and the high density of fast states at the Si-sapphire interface.

Oscillatory Subthreshold Responses and Potential Fluctuation Observed in Squid Giant Axons

Abstract: The process of development of the hard-mode instability has been studied in sensitized squid axons by measuring (1) Fourier spectra of fluctuating voltages, (2) subthreshold oscillations of the membrane potential induced by weak current pulses, and (3) membrane potential changes induced by weak sinusoidal current. It was found that the observed spectra could be explained satisfactorily on the basis of the theory of irreversible circulation of fluctuation developed by Tomita and that the linear response theory formulated by Kubo was applicable to the membrane system far from thermodynamic equilibrium.

Constant voltage threshold device

Abstract: Disclosed is a constant voltage threshold device for providing a substantially constant voltage across a pair of terminals. The threshold device includes a field effect device having source and drain regions formed into an isolated semiconductor region which, in turn, is formed into a substrate. The distance between the drain region of the field effect device and the substrate is directly related to the threshold voltage of the threshold device. The threshold voltage is also determined by the relative doping levels of the various semiconductor regions and the value of various fixed biasing potentials applied to the various electrodes of the threshold device.

Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation

Abstract: Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with L EFF = 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.

Long-tailed-pair connections of MOSFET's operated in sub-threshold region

Abstract: Long-tailed pair connections of MOSFET's are used as voltage comparators, the input stages of operational amplifiers, and other circuitry where their nearly infinite gate impedances can reduce the loading upon preceding circuitry. As conventionally operated, the tail current caused to flow through the interconnected source electrodes of the MOSFET's is sufficient to bias them such that their source-to-gate voltages exceed a threshold voltage, and the input voltage offset error of the long-tailed MOSFET pair is likely to be higher than that of most long-tailed bipolar transistor pairs. By selecting a tail current that is sufficiently small to operate a long-tailed MOSFET pair such that their source-to-gate voltages are in the sub-threshold region, the MOSFET's exhibit exponential drain current versus source-to-gate characteristics which result in markedly reduced input offset voltage error.

Fabrication and properties of ESFI-SOS-MOST's suitable for both low-voltage and low-power circuits

Abstract: The fabrication and the properties of ESFI-SOS p-channel deep-depletion and n-channel inversion transistors are discussed. These devices are aimed to be used in integrated circuits with both low supply voltage and low power consumption. It turns out that certain device parameters such as reverse current, leakage current, threshold voltage, and channel mobility are strongly correlated and that a proper set of process parameters (e.g., optimum process temperature, ion implantation dose, and implantation energy) exists permitting device fabrication most suitable to meet the goal mentioned above. Furthermore, the subthreshold behavior is investigated experimentally and theoretically and the density of fast interface states at the SiO 2 -Si interface is determined.

Convexity theorem for subthreshold stimuli in linear models of visual contrast detection

Abstract: Under the general assumption that visual contrast detection occurs by a parallel array of linear detectors, either without probability summation or with probability summation of a commonly assumed type, it is shown that the set of functions representing subthreshold stimuli must be convex. Thus, for example, a planar plot of the threshold locus using multiples of any two functions as axes, must be convex (cannot bulge inward). If experimental evidence to the contrary were discovered, it would rule out detection by parallel linear detectors of the above type. One possible kind of such evidence would be an inward cusp of the threshold locus corresponding to one of a special class of stimuli to which the visual system might be specifically sensitive.

Subthreshold behaviour of e.s.f.i.-s.o.s. transistors

Abstract: Theoretical and experimental results are presented which illustrate the influence of various parameters on the subthreshold behaviour of e.s.f.i.-s.o.s. transistors. The numerical analysis accounts for the thin silicon film and the existence of a second interface. A comparison is made with a corresponding bulk transistor, furthermore, between a two- and a one-dimensional analysis of e.s.f.i.-s.o.s. m.o.s.t. The agreement for real cases is found to be excellent.

Suppression of Anomalous Drain Current in Short Channel MOSFET

Abstract: The current voltage characteristics of short channel nMOSFET in the subthreshold region is investigated by two-dimensional numerical analysis. Deep ion implantation of acceptor impurities beneath the channel is found to improve the subthreshold characteristics. Structure optimization for the deeply ion-implanted short channel MOSFET is carried out to obtain low subthreshold current with steep semilogarithmic slope, which are almost comparable with the long channel MOSFET.

Effects of subthreshold fission on neutron dose measurements made with 237Np detectors.

Abstract: Although the fission cross section of 237Np has a “threshold” at about 200 keV, it is still significant at lower energies. To facilitate corrections of 237Np dosimeter readings for this subthreshold response, recently measured cross sections between 1 and lo5 eV have been approximated by an analytical function of energy. This was used to calculate the contribution of subthreshold neutrons to the response of Np dosimeter for measurements of fission neutrons transmitted through various materials. For most of the spectra, the effect was less than 3%, but for some it was several times larger. The fission resonance integral, from 0.5 eV to 100 keV. is 280 mb.

High-accuracy extraction of buried-channel m.o.s. transistor threshold voltages

Abstract: A new experimental method is presented, which yields threshold voltages and their dependence on substrate bias for buried-channel, usually ion-implanted m.o.s. transistors with an accuracy typically < 10 mV. The extraction follows from two current measurements in the linear region, one as a function of gate voltage and fixed substrate bias, the other as a function of substrate bias roughly at the flat-band voltage.

Substrate-fed CMOS memory device

Abstract: A novel structure of a negative resistance diode for high density static RAM cell is described. The diode, called Substrate-Fed CMOS (SF-CMOS) diode, consists of weak depletion type p- and n-MOSTs, whose drains are formed in the p-well and n-substrate, respectively. The structure enables supplying a diode current via substrate. Drain currents for the FETs, which operate in the subthreshold region, are controlled by back-gate bias, resulting in a sharp negative resistance with an "OFF" current below 1pA. The SF-CMOS diode plus a transfer-gate transistor and a load element make up a memory cell. The feasibility of using a polysilicon resistor, a leaky diode and a MOSFET for the load element is discussed. An eight-by-eight cell array of SF-CMOS cells with MOSFET loads is fabricated and examined. Using a 5µm line width and 3µm spacing design rule, the obtained cell size is 1440µm2, compared with 3000µm2required for a six-transistor cell. A 4096-word by 1-bit static RAM has been designed using SF-CMOS cells. The obtained chip size is as small as 14.9mm2. READ and WRITE operations of the RAM are similar to those of single transistor cells, except that SF-CMOS cells need no refresh operation. A 45 ns access time has been obtained with 5-volt V DD , using computer simulation.

Subthreshold velocity‐field characteristic of n‐type indium phosphide at 77 K

Abstract: Measurements of the subthreshold velocity‐field characteristic at 77 K using a direct technique show reasonable agreement with theoretical predictions, but show a lower threshold field. Comparisons of threshold values of field and velocity with extrapolations from other measured and theoretical data are favorable.