Showing papers on "Subthreshold conduction published in 1986"
TL;DR: In this article, the authors showed that the sub-threshold slope of transistors made in thin silicon films can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel.
Abstract: Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel For comparison, the subthreshold slope of transistors made in thicker films is also reported
263 citations
TL;DR: In this article, an analytical dc model for the MODFET was proposed that makes use of a new approximation of the 2DEG concentration versus gate-to-channel voltage, which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation.
Abstract: We present an analytical dc model for the MODFET that offers several improvements over existing models. An enhanced version of the model makes use of a new approximation of the two-dimensional electron gas (2DEG) concentration versus gate-to-channel voltage, which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. Even in this more accurate model there are no complicated numerical calculations involved; at most what is required is finding a single root of a function of one variable. We propose an electron velocity-field curve that combines the observed field-dependent mobility in the 2DEG, and the sharp velocity saturation in GaAs. We use a two-region Grebene-Ghandhi model with floating boundary for the channel. The quasi-linear region on the source side is treated by the gradual channel approximation and extends toward the drain up to a point where the field reaches its threshold for velocity saturation. Between this point and the drain-side end of the channel, the potential is determined by the two-dimensional Poisson equation in the AlGaAs region. The resuiting I-V characteristics and their slopes are continuous. The model predicts a maximum transconductance and a finite intrinsic output conductance in the saturated region, two features experimentally observed but not predicted by previous models. In the limit of very short gate lengths the model approaches the saturated velocity model, while in the limit of very long gate lengths it approaches the classical gradual channel model.
102 citations
TL;DR: In this paper, it has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can have very steep slopes in the subthreshold region.
Abstract: It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can have \log (I_{d}): V_{gs} , characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.
85 citations
TL;DR: In this article, the temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics, due to differences in gate contact potential and anomalies of the substrate backbias effect.
Abstract: The temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics. Owing to differences in gate contact potential and anomalies of the substrate backbias effect, the above coefficient has a typical value for each type. In particular for a compensated device, such as a CMOS p-channel MOSFET, the value of the temperature coefficient is relatively large (up to 3 mV/degree).
66 citations
TL;DR: In this article, a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and sub-threshold current.
Abstract: In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions The validity of these published expressions has not been verified so far for small-geometry devices of different parameters Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values Hence we determined a set of new geometry parameters η and B/A for the DIBL threshold relationship that can be used with the analytical model Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required Also, our results should be useful for calibrating existing analytical MOSFET models In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices
65 citations
TL;DR: A physical model that characterizes the subthreshold drain current (gatevoltage swing) and threshold voltage of thin-film LPCVD polysilicon MOSFET's is developed and supported experimentally.
Abstract: A physical model that characterizes the subthreshold drain current (gate-voltage swing) and the threshold voltage of thin-film LPCVD polysilicon MOSFET's is developed and supported experimentally. The model describes the influence of the grain boundaries and of the charge coupling between the front and back gates on the subthreshold behavior. Main predictions are that the gate-voltage swing depends strongly on grain-boundary properties but weakly on the charge-coupling effects, that the threshold voltage depends strongly on grain-boundary properties and charge-coupling effects, and that the charge-coupling effects diminish as the grain-boundary trap density, the thickness of the film, or the doping density in the film increases. Comparisons of model predictions and measured data for passivated (hydrogenated) and unpassivated devices indicate quantitatively how hydrogenation reduces the trap density and increases the carrier mobility in the channel.
36 citations
TL;DR: In this article, a modification to the sub-threshold measurement technique of McWhorter and Winokur is proposed for oxides in which these donor states occur, and less interface dose enhancement occurs during x-ray exposures than was observed previously with thickoxide-capacitor measurements.
Abstract: Transistor behavior in the subthreshold region is used to compare the production of oxide trapped charge and interface states produced by x-ray and Co-60 radiation. For the oxides used in this study, the subthreshold data indicates the presence of two types of interface states. One of these interface states appears to differ from the more commonly observed amphoteric defect. The characteristics of these states suggest that they are donor defects. These states further complicate testing protocols because they anneal at room temperature. A modification to the subthreshold measurement technique of McWhorter and Winokur is proposed for oxides in which these donor states occur. Using this revised subthreshold technique, less interface dose enhancement occurs during x-ray exposures than was observed previously with thick-oxide-capacitor measurements.
19 citations
TL;DR: In this paper, the influence of optical radiation on the MOSFET threshold voltage has been investigated theoretically as well as experimentally, and the relation between the threshold voltage and the optical radiation intensity has been derived.
18 citations
IBM1
TL;DR: An As-P double-diffused lightly doped drain (LDD) device was designed and fabricated with a self-aligned titanium disilicide process, and the device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current as mentioned in this paper.
Abstract: An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.
18 citations
TL;DR: In this article, a simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region was derived.
Abstract: A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.
18 citations
TL;DR: In this paper, a microwave-excited plasma oxidation technique is applied to gate oxide formation of MOSFET's and subsequent processes are carried out essentially at temperatures below 600°C.
Abstract: A microwave-excited plasma oxidation technique is applied to gate oxide formation of MOSFET's and subsequent processes are carried out essentially at temperatures below 600°C. These MOSFET's compare favorably with conventional ones fabricated by using a high-temperature processes in terms of field-effect mobility and subthreshold characteristics.
TL;DR: In this article, an analytical model for sub-threshold current for both long-channel and short-channel MOSFET's is presented, where the analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used.
Abstract: In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.
TL;DR: In this paper, a rate equation has been used to analyze the actively mode-locked diode laser which is biased with a subthreshold dc current upon which a sinusoidal signal, whose frequency is equal to the mode spacing (or its multiple) of the external cavity, is superimposed.
Abstract: A rate equation has been used to analyze the actively mode-locked diode laser which is biased with a subthreshold dc current upon which a sinusoidal signal, whose frequency is equal to the mode spacing (or its multiple) of the external cavity, is superimposed. Steady-state operation of the laser enables us to find out many important parameters of the system. Based upon the experimental observations, we have established the time evolution of the injection carrier density which suggests the existence of a subpulse following the main pulse and provides the possibility of predicting the time gap between them. Meanwhile, the average output power of the laser, the threshold condition of the mode-locked oscillator, the arrival time of the main pulse at the gain medium, the temporal difference between the main pulse, and the peak of the small-signal gain have also been derived.
Patent•
10 Dec 1986TL;DR: In this paper, a voltage controlled oscillator (VCO) has an LC tank circuit which is pumped by two out-of-phase feedback components, and the combined effect of these two feedback components results in an effective feedback signal that is a function of the ratio of the magnitude of the two out ofphase coponents.
Abstract: A voltage controlled oscillator (VCO) has an LC tank circuit which is pumped by two out-of-phase feedback components. The combined effect of the two out-of-phase feedback components results in an effective feedback signal that is a function of the ratio of the magnitude of the two out-of-phase coponents. The magnitude of one of these feedback components is controlled by a CMOS subthreshold Gilbert multiplier. The frequency of oscillation of an oscillating signal within the LC tank circuit changes according to a control voltage applied to the Gilbert multiplier.
TL;DR: In this article, a simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure, and the results match the experimental data.
Abstract: A simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure. It predicts both the short-channel and the narrow-width effects on the threshold voltage of MOSFET's, and the results match the experimental data. In addition, the threshold expression is more general than any other existing models. It includes all the relevant device parameters, such as the drain voltage, the oxide and surface charges, and the fringe field through the oxide sidewalls.
TL;DR: In this paper, a test is made of a recent proposal by Lewyn and Meindl for approximation of MOS inversion layer charge and substrate capacitance, which includes the pinning of the depletion layer width in strong inversion.
Abstract: A test is made of a recent proposal by Lewyn and Meindl for approximation of MOS inversion layer charge and substrate capacitance. Included in the test are the charge sheet formula and a new formula derived here which includes the pinning of the depletion layer width in strong inversion. Comparison with numerical calculation shows the Lewyn-Meindl result for charge density is less accurate than the charge sheet result over the entire subthreshold region. Similar inaccuracy is expected in MOS current-voltage curves in the subthreshold region and near pinch-off. The new formula is better than the other two over the entire bias range. A comparison of dc and ac substrate capacitances shows the new result to be better than both of the other formulas. In inversion, however, the percent error in dc capacitance is large. This large percent error corresponds to a small absolute error because the dc capacitance goes to zero in strong inversion. The ac capacitance error in strong inversion is ∼5 percent because of neglect of the ac inversion layer redistribution. Percent error curves for all three formulas are presented as a function of band bending and reverse bias.
TL;DR: In this paper, an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs is presented.
Abstract: This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.
TL;DR: In this paper, the relative mode intensities in the hybrid CO2 laser output are investigated for sub-threshold operation of cw gain section and the rate equation model developed for the purpose provides estimates in very satisfactory agreement with experimental results.
Abstract: The relative mode intensities in the hybrid CO2 laser output are investigated for subthreshold operation of cw gain section. The rate equation model developed for the purpose provides estimates in very satisfactory agreement with experimental results. The model also predicts the existence of an optimum pressure and length for the cw discharge section and shows that very good longitudinal mode discrimination is possible even when cw discharge section gain is only a tenth of that required for oscillation.
TL;DR: In this article, the response of the SQUID to an external magnetic flux that includes dc, periodic, and stochastic components is determined as a function of the internal parameters of the device.
Abstract: We consider a rf SQUID subjected to an external magnetic flux that includes dc, periodic, and stochastic components. Using a previously developed linearization technique, the response of the SQUID (below its hysteresis threshold) to this force is determined as a function of the internal parameters of the device. The measurement process, wherein the flux sensed by the SQUID is coupled to a tank circuit, is also considered. The results obtained, using the linearization technique referred to above, are compared with previously reported work on this subject. It is seen that, while not exact, this technique allows one to compute, analytically, the response (measured as an autocorrelation function or its associated spectral density) very accurately below the SQUID hysteresis threshold.
TL;DR: In this paper, the authors investigated the origin of the sub-threshold leakage current in self-aligned gate GaAs MESFETs using temperature characterization, the leakage current was found to be comprised of two components, each dominant in a different temperature range.
Abstract: The origin of the subthreshold leakage current in self-aligned gate GaAs MESFET's is investigated using temperature characterization, The leakage current is found to be comprised of two components, each dominant in a different temperature range. At temperatures below 0°C, space-charge-limited injection through the surface of the depleted channel dominates. At room temperature and above, the leakage current measured is the ohmic leakage through the bulk substrate. The space-charge-limited injection current is also found to be sensitive to the GaAs substrate quality.
TL;DR: In this article, the authors used low-temperature processing to minimize dopant diffusion along subboundaries in the graphite-strip-heater (GSH) silicon-on-insulator (SOI) films.
Abstract: CMOS devices with effective channel lengths ranging from 0.7 to 4.0 µm have been fabricated in zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) films prepared by the graphite-strip-heater technique. Low-temperature processing was utilized to minimize dopant diffusion along subboundaries in the films. Both n- and p-channel devices have low leakage current (<0.1-pA/µm channel width) and good subthreshold characteristics. For ring oscillators with a transistor channel length of 0.8 µm, the propagation delay is 95 ps at a supply voltage of 5 V.
TL;DR: In this paper, a two-dimensional numerical process and device simulation is presented to obtain the subthreshold characteristics of narrow-width MOSFETs, where the process simulator calculates the doping distribution in the width direction on the basis of technology data.
Abstract: A two-dimensional numerical process and device simulation is presented to obtain the subthreshold characteristics of narrow-width MOSFETs. The process simulator calculates the doping distribution in the width direction on the basis of technology data. The device simulator determines the electrical characteristics using the calculated doping profile. Calculated and measured data on the threshold voltage as a function of the channel width agree well.
TL;DR: In the subthreshold region of JFETs, a reach-through diode is formed between the top and bottom gates as mentioned in this paper, which has consequences for the application of separated-gate JFCE.
Abstract: In the subthreshold region of JFETs a reach-through diode is formed between the top and bottom gates. This has consequences for the application of separated-gate JFETs.
TL;DR: In this article, the authors investigated the effect of short channel effects and hot carrier related instabilities on MOSFETs and concluded that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFs are technologically incompatible.
Abstract: Enhancement and depletion mode n -channel MOSFETs are investigated with respect to short channel effects and hot carrier related instabilities. It is found that subthreshold characteristics of normally off type devices are improved by additional deep channel implants. However, long term stability of enhancement mode devices decreases with the deep channel implant dose. A similar behavior is observed for depletion mode devices. Significant improvement in device stability can be realized using buried channel conduction. However, short channel effects attain untolerable magnitudes in devices with deep buried channels. It is concluded in this paper, that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFETs are technologically incompatible. In the outlook, device design requirements are discussed to circumvent these problems.
TL;DR: A new composite two-dimensional process/two-dimensional device simulation system (TOP-MODE) has been developed to provide a straightforward means of predicting small-geometry device characteristics using the fabrication process sequence.
Abstract: A new composite two-dimensional process/two-dimensional device simulation system (TOPMODE) (FOOTNOTE: Standing for TOshiba Simulation Program for MOS DEvice.) has been developed to provide a straightforward means of predicting small-geometry device characteristics using the fabrication process sequence. Using TOP-MODE, an analysis of the anomalous subthreshold drain current peculiar to buried oxide isolation (BOX) structure device has been conducted and the physical mechanism is attributed to the impurity profile and other geometry effects. Input to TOPMODE is specially designed using key words language as a user-oriented CAD tool. Plotting functions for multidimensional perspective drawing of output results have also been installed to provide a better visual aid.
IBM1
TL;DR: In this article, hot electron induced MOSFET instabilities have been found to significantly degrade the retention time of dynamic RAMs. Failure is due to the effect of increased subthreshold leakage on balanced sense nodes.
Abstract: Hot electron induced MOSFET instabilities have been found to significantly degrade the retention time of dynamic RAMs. Failure is due to the effect of increased subthreshold leakage on balanced sense nodes. Plasma nitride passivations greatly increase the degradation rate. The complex synergism between device degradation and DRAM parametric shift demonstrates the necessity of accelerated stress of functional modules.