Showing papers on "Subthreshold conduction published in 1996"

Cloning of a novel component of A-type K+ channels operating at subthreshold potentials with unique expression in heart and brain.

Abstract: 1. Proteins of the Kv4 or Shal-related subfamily are key components of transient K+ channels (A channels) operating at subthreshold values of the membrane potential. We have cloned and characterize...

Translinear circuits in subthreshold MOS

Abstract: In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI “translinear system” with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.

Unified complete MOSFET model for analysis of digital and analog circuits

Abstract: In this paper, we describe a complete MOSFET model developed for circuit simulation based on fully consistent physical concept. The model describes all transistor characteristics as a function of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. Contrary to the expectation, the results show that our semi-implicit model including the iteration procedures can even reduce the CPU time significantly in comparison with a conventional model similar to BSIM2 including short-channel effects. This is due to the consistent description of the model equations for all transistor characteristics, which results in more straightforward device equations, once the surface potentials have been computed.

Subthreshold dynamics in periodically stimulated squid giant axons.

Abstract: Action potentials resulting from periodic stimulation of nerve axons occur at intervals that are irregular at moderate stimulation frequencies. Histograms of the intervals are multimodal, as seen in stochastic resonance. At higher stimulation frequencies, the action potentials are suppressed entirely, leaving only subthreshold dynamics. Return maps constructed from data show that both types of response are governed by the same deterministic one-dimensional description, with an unstable subthreshold fixed point largely accounting for the irregular intervals at moderate stimulation frequencies. [S0031-9007(96)00200-1]

Translinear circuits using subthreshold floating-gate MOS transistors

Abstract: We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.

Low voltage CMOS logic circuit with threshold voltage control

Abstract: A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits are connected between a low threshold voltage CMOS circuit and a supply voltage and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs in the MOSFET circuits are gate biased by low threshold voltage MOSFETs, thereby preventing a current from flowing across the backgate terminal and the source terminal.

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

Abstract: Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V/sub th/, we derived a model for V/sub th/ of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, /spl Delta/V/sub th/, and subthreshold swing (S-swing) degradation with decreasing gate length L/sub G/, and showed that we can design a 0.05-/spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available.

A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling

Abstract: In this paper we present a new theoretical approach in MOS modeling to derive analytical, physics-based model equations for the geometry and voltage dependence of threshold voltage and for the subthreshold behavior of short-channel MOSFETs. Our approach uses conformal mapping techniques to analytically solve the two-dimensional Poisson equation, whereby inhomogeneous substrate doping is taken into account. The presented model consists of analytical equations in closed form and uses only physically meaningful parameters. Therefore, the results are not only useful in circuit simulators but also in calculations of scaling behavior, where planned processes can be investigated. Comparison with numerical device simulation results and measurements confirm the high accuracy of the presented model.

Enhancement of neural synchronization in computational models of ventral cochlear nucleus bushy cells

Abstract: Ventral cochlear nucleus (VCN) bushy cells, especially globular bushy cells (GBCs), show enhanced synchronization to low-frequency tones (<1 kHz) when compared to auditory nerve (AN) fibers. Joris and colleagues (J. Neurophysiol. 71:1022, 1994) interpreted the enhanced synchronization as implying that GBCs receive multiple AN inputs which are individually subthreshold, so that the enhancement results from the necessity for coincidence of input spikes in order to produce an output spike. By contrast, in a previous modeling study, we concluded that high-BF GBCs must receive suprathreshold inputs in order that their spike trains be irregular and in order that they synchronize strongly in the midfrequency range (1-5 kHz). In this study, we reconsider the modeling results in an attempt to account for enhanced synchrony in models which display all the properties of bushy cells; the principal variables studied are the number and strength of synaptic inputs. A simple shot-noise threshold model displays enhanced synchronization at 500 Hz with either subthreshold or suprathreshold inputs. A membrane-conductance model, which accurately reproduces bushy-cell electrical characteristics, displays enhanced synchronization at low frequencies with a variety of input configurations. These configurations differ in their spontaneous activity, regularity, PST histogram shape, and mid-frequency phase-locking. Models with all subthreshold or all suprathreshold inputs each match some aspects of GBC behavior, but neither model reproduces all aspects: subthreshold models phase-lock more weakly at mid-frequencies than almost all the GBC data and suprathreshold models have inappropriate PST histogram shapes and spontaneous rates that are too high. A model which better reproduces average GBC data has suprathreshold inputs combined with a tonic inhibitory input. However, the modeling results, taken as a whole, suggest that there must be subclasses of GBCs with different arrangements of synaptic input, including both subthreshold and suprathreshold inputs.

Short-channel effect immunity and current capability of sub-0.1-micron MOSFET's using a recessed channel

Abstract: Sub-0.1-/spl mu/m planar and gate recessed MOSFET's are investigated using both drift-diffusion and Monte Carlo simulations. In nonplanar devices, the influence of the gate corner explains that the threshold voltage roll-off can be almost suppressed. A steeper subthreshold slope (low swing) is also obtained for a channel length shorter than 50 nm when the recessed channel MOSFET is compared to its planar counterpart. The influence of the corner effect on high-current performances is also considered in relation with the electric field profile along the Si/SiO/sub 2/ interface.

Iddq testing for high performance CMOS-the next ten years

Abstract: CMOS scaling affects the subthreshold current per IC, and it directly impacts the utility of Iddq testing for CMOS devices. Continued IC manufacturing refinements enable a factor of /spl radic/2 reduction in line widths every three years. This in conjunction with an increase in chip size makes it possible to increase the number of transistors per IC by a factor between two and three. This trend in CMOS technology is expected to continue over at least the next ten years. The scaling of devices affects numerous device parameters, one being the subthreshold current commonly known as the leakage current. Assuming defect size scales with technology, it will be explained why it will become increasingly difficult to differentiate good and defective devices based upon an Iddq test methodology.

Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs

Abstract: Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift /spl Delta/Vth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 /spl mu/m L/sub G/ device of which threshold voltage is 0.2 V, /spl Delta/Vth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI.

Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs

Abstract: The applicability of charge-pumping technique to characterize the oxide/silicon interface in standard power Vertical Double-diffused (VD)MOS transistors is studied. Qualitative analysis of the charge-pumping threshold and flat-band voltage distributions in the VDMOS structure, supported with rigorous transient numerical modeling of the charge-pumping effect, shows that the measurements can be carried out in the subthreshold region. This conclusion is confirmed by various experimental results. The characteristics, i.e. charge-pumping current versus gate top level, is studied in detail. The changes in the characteristics after /spl gamma/-ray irradiation are analyzed. A charge-pumping-based method for separate extraction of interface state density and density of charge trapped in the oxide after irradiation of VDMOSFETs is proposed. The validity and limitations of the method are studied by experiments and modeling.

A four-quadrant subthreshold mode multiplier for analog neural-network applications

Abstract: A new four-quadrant CMOS analog multiplier is presented, based on devices operating in the subthreshold mode of conduction. The proposed circuit is a cross-coupled quad structure in which differential multiplication is obtained by driving the gate and bulk (back gate) terminals of the devices. Analysis and simulation have shown that the new structure has the characteristics required for the design of very large scale integration (VLSI) analog neural networks. Although operating at subthreshold current levels, reasonable speed can be obtained since voltage swings are in the range of a few V/sub t/. The behavior of the basic multiplier has been assessed experimentally using transistor-arrays and simulation studies on a network including 11 neurons and 31 synapses indicate a useful level of functionality.

Suppression of threshold voltage variation in MTCMOS/SIMOX circuit operating below 0.5 V

Abstract: We describe a power-switch transistor for a multi-threshold CMOS/SIMOX circuit operating at extremely low supply voltage below 0.5 V. Power-switch transistors with a gate-body-connected variable-threshold MOSFET and a conventional MOSFET were fabricated and measured. The variable-threshold MOSFET suppressed the variation in threshold voltage and improved current drivability. Suppression of variation in gate delay time and improvement in the delay time were demonstrated at low supply voltage below 0.5 V.

Control and analysis of leakage currents in poly‐Si thin‐film transistors

Abstract: Control of leakage current in autoregistered columnar and a solid phase crystallized poly‐Si thin‐film transistors(TFTs) is discussed. For n‐channel TFTs, two parasitic leakage current paths, due to bulk conduction and back interface conduction, have been identified. It is demonstrated that these can be controlled by using sufficiently thin films and by low dose boron back channel implants, respectively. By these means, generation limited leakage currents, with values of <4×10−14 A/μm of channel width, have been obtained. The minimum leakage currents, for n‐ and p‐channel TFTs, display the well‐known field enhancement which we confirm can be described by phonon assisted tunneling. In well‐engineered TFTs, with subthreshold slopes of <1 V/dec, we show that the drain fields required to promote the tunneling process are independent of the trap state density and result entirely from two‐dimensional gate‐drain coupling effects. Therefore, improving the quality of the poly‐Si will not reduce the exponential dependence of the leakage current on gate and drain bias, although the absolute value of leakage current will be reduced.

Method of erasing a flash EEPROM memory cell array optimized for low power consumption

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

Selectively grown vertical Si-p MOS transistor with short channel lengths

Abstract: Vertical p-MOS transistors with channel lengths of ~130 nm have been fabricated using selective LPCVD epitaxy for the definition of the channel region, instead of fine line lithography. Owing to self-aligned facet growth the channel region and the volume diode which limited the parasitic bipolar transistor can be designed more independently. Thus a short-channel p-MOS transistor with a high breakthrough voltage, an ideal subthreshold behaviour and a high transconductance was fabricated.

Nonvolatile semiconductor memory device for storing multi-value data

Abstract: Each of the cell transistors which constitute an EEPROM is set one of the first to fourth threshold voltages, to store one of four different data items. The first and fourth threshold voltages are the lowest and the highest of the four, respectively, and the second threshold voltage is lower than the third threshold voltage. Each cell transistor is set at a neutral threshold voltage when the charge-accumulating layer accumulates no charge. The neutral threshold voltage is higher than the second threshold voltage and lower than the third threshold voltage. The difference between the neutral threshold voltage and one of the four threshold voltages is so small that the self-field of the cell transistor has a low intensity.

Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 /spl mu/m thick silicon pillars

Abstract: Fabrication of MOSFETs on the sidewall of ultra-thin silicon pillars has been shown. The structures employ a self-aligned drain to enable the use of minimum definable pillar widths. Additionally by moving to a vertical structure, the high current density of surrounding gate MOSFETs can be achieved on conventional bulk substrates, and self-aligned gates can be maintained. These devices exhibit near ideal subthreshold slopes and low DIBL values, making them ideal for low power applications.

An analog floating-gate memory in a standard digital technology

Abstract: In this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based on a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the memory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results from test chips fabricated in a standard 2-micron CMOS process show six orders of magnitude dynamic range in current for subthreshold operation.

An analytical moderate inversion drain current model for polycrystalline silicon thin‐film transistors considering deep and tail states in the grain boundary

Abstract: This paper presents an analytical moderate inversion drain current model for polycrystalline silicon thin‐film transistors based on localized deep and tail states in the grain boundary regions. As verified by the published data, using the analytical model, that as compared to the subthreshold region in the bulk iliccon metal‐oxide‐silicon (MOS) devices, the less steep slope of the moderate inversion region has been explained as due to the lowering in the potential barrier height. In addition, the analytical model provides an accurate prediction that with a smaller average trap state density from the grain boundary regions, the polysilicon thin‐film transistor shows a sharper moderate inversion behavior.

Unified physical I-V model including self-heating effect for fully depleted SOI/MOSFET's

Abstract: A physically based analytical I-V model that includes self-heating effect (SHE) is presented for fully depleted SOI/MOSFET's. The incorporation of SHE is done self-consistently in a fully closed form, making the model very suitable for use in circuit simulators. The model also accounts for the drain induced conductivity enhancement (DICE) and drain induced barrier lowering (DIBL), channel length modulation (CLM), as well as parasitic series resistances (PSR). Another advantage is the unified form of the model that allows us to describe the subthreshold, the near-threshold and the above-threshold regimes of operation in one continuous expression. A continuous transition of current and conductance from the linear to the saturation regimes is also assured. The model shows good agreement with measured data for a wide range of channel lengths (down to 0.28 /spl mu/m) and film thicknesses (94 nm-162 nm).

A novel 0.1 μm MOSFET structure with inverted sidewall and recessed channel

Abstract: To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V/sub D/=2 V is 446 mS/mm for the 0.1 /spl mu/m n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 /spl mu/m to 0.1 /spl mu/m and good subthreshold characteristics are achieved for 0.1 /spl mu/m channel device.

A wide dynamic range continuously adjustable CMOS current mirror

Abstract: A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current.

Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories

Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide or interpoly dielectric of EPROM, EEPROM and flash-EEPROM memories.

Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-mode applications

Abstract: Low-frequency (1/f) noise has been characterized for the first time in TFSOI BiCMOS devices designed for low power high frequency applications. In the bipolar transistors, 1/f noise obeyed a square law dependence on base current and was proportional to the inverse of the area. Aside from the expected 1/f noise, we have also observed a bias dependent generation-recombination (G/R) noise component in a small portion of these TFSOI BJTs. The 1/f noise in the near-fully-depleted MOSFETs was found to be bias independent in both the linear and saturation region of operation. However, when operated in the subthreshold regime, extraneous generation-recombination (G/R) noise becomes apparent.

Low voltage and low frequency current mirror using a two-MOS subthreshold op amp

Abstract: The authors describe a novel current mirror for low voltage and low frequency application, which uses an op amp with only two MOS transistors operating in the weak inversion region. The advantages of the circuit are low voltage operation, small chip area, high output resistance and no bias current (voltage). The proposed circuit is confirmed by SPICE simulation.

Effects of random MOSFET parameter fluctuations on total power consumption

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultra-small-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte-Carlo simulator. These fluctuations are shown to pose fundamental barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation in multi-billion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard-maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40-600 mV, 10-100%, 2-20 mV/dec. and 10-10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V CMOS technology generation with 1.3-64 billion transistors on a chip. While these limits can be transcended to some degree by selecting optimal transistor width values larger than the channel length, the associated penalties in dynamic and static power, and in packing density demand novel MOSFET designs aimed at minimizing these fluctuations.

Memory cell having asymmetrical source/drain pass transistors and method for operating same

Abstract: A memory cell having an asymmetrical transistor which provides access to a data storage circuit of the memory cell. The asymmetrical transistor exhibits a forward threshold voltage when forward biased and a reverse threshold voltage when reverse biased. The forward threshold voltage is less than the reverse threshold voltage. The asymmetrical transistor is connected such that during write-disturb mode, the asymmetrical transistor is reverse biased to provide a relatively high reverse threshold voltage. This high reverse threshold voltage minimizes subthreshold current leakage during write-disturb mode, thereby reducing the possibility of data corruption. During read mode, the asymmetrical transistor is forward biased to provide a relatively low forward threshold voltage. This low forward threshold voltage maximizes the read voltage applied to the data storage circuit through the asymmetrical transistor, thereby improving the stability of the memory cell.