Showing papers on "Subthreshold conduction published in 1997"

Autonomous stochastic resonance in bursting neurons

Abstract: Noise-induced firing is studied in two major classes of bursting neuron models in the absence of periodic input. In the biologically relevant subthreshold regime where no deterministic firing occurs, additive noise induces spiking limit cycles. This noise makes the output firing patterns sensitive to the characteristics of autonomous subthreshold oscillations, which can change in response to various physicochemical stimuli. The nonmonotonic behavior with increasing noise of the phase locking between spikes and subthreshold oscillations, measured using spectral signal-to-noise ratios and line shape characteristics, are a manifestation of autonomous stochastic resonance in these systems. The type of bifurcation giving rise to bursting activity determines the behavior with noise of the mean firing frequency, interspike interval histogram, spike train power spectrum, and phase locking. In particular, it is shown that a saddle-node bifurcation is not required to see stochastic resonance ~SR! without periodic input when there exists a stable deterministic subthreshold oscillation. This paper also studies SR in a detailed ionic neuron model, an approach that leads to tests of hypotheses regarding the nature of noise in real neurons. @S1063-651X~97!12001-3#

Intrinsic MOSFET parameter fluctuations due to random dopant placement

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.

AlGaN/GaN HEMTs grown on SiC substrates

Abstract: The fabrication and characterisation of AlGaN/GaN HEMTs grown on SiC substrates are described. These devices have a transconductance of 70 mS/mm and a gate breakdown voltage in excess of 100V. The HEMTs have a hard pinch-off with nearly ideal subthreshold characteristics. An f/sub T/ of 6 GHz and an f/sub max/ of 11 GHz were measured for 1 /spl mu/m gate length devices.

Inversion of the current-distance relationship by transient depolarization

Abstract: The objective of this research was to develop a technique to excite selectively nerve fibers distant from an electrode without exciting nerve fibers close to the electrode. The shape of the stimulus current waveform was designed based on the nonlinear conductance properties of neuronal sodium channels. Models of mammalian peripheral myelinated axons and experimental measurements on cat sciatic nerve were used to determine the effects of subthreshold polarization on neural excitability and recruitment. Subthreshold membrane depolarization generated a transient decrease in neural excitability and thus an increase in the threshold for stimulation by a subsequent stimulus pulse. The decrease in excitability increased as the duration and amplitude of the subthreshold depolarization were increased, and the increase in threshold was greater for fibers close to the electrode. When a depolarizing stimulus pulse was applied immediately after the subthreshold depolarization, nerve fibers far from the electrode could be stimulated without stimulating fibers close to the electrode. Subthreshold depolarizing prepulses inverted the current-distance relationship and allowed selective stimulation of nerve fibers far from the electrode.

Back-gated CMOS on SOIAS for dynamic threshold voltage control

Abstract: The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.

Technology challenges for integration near and below 0.1 /spl mu/m

Abstract: Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.

Active pixel sensor using CMOS technology with reverse biased photodiodes

Abstract: An active pixel sensor implemented with CMOS technology that employs a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods. The transistors in the switching network operate in a forward active subthreshold region, ensuring linear operation and the diode voltage is clamped to a small positive voltage so that the diode is always reverse-biased. A source-follower generates a output signal correlated to the charge on the storage node that is coupled to column output circuitry that samples the signal. An operational scheme is employed wherein the storage node is first set to a defined voltage, the photocurrent is allowed to discharge the storage node and then the remaining charge coupled as a first signal to the column output circuitry, which samples and stores the first signal. The storage node is then reset to the same defined voltage and the resulting charge on the storage node is coupled as a second signal to the column output circuitry. The column output circuitry computes the difference of the first and second signals, which provides a reliable measure of the photocurrent during the integration period.

A realistic large-signal MESFET model for SPICE

Abstract: A comprehensive large-signal MESFET model that provides a realistic description of measured characteristics over all operating regions is presented, It describes subthreshold conduction and breakdown. It has frequency dispersion of both transconductance and drain conductance, and derates with power dissipation. All derivatives are continuous for a realistic description of circuit distortion and intermodulation. The model has improved descriptions of capacitance and bias dependence. It has small-signal S-parameter accuracy extended to a wide range of operating conditions. The model is implemented with new techniques for continuity and dispersion. These provide accurate prediction of circuit performance and also improve simulation speed.

Fatigue laser-induced damage in transparent materials

Abstract: We discuss the damage in transparent dielectrics produced by a train of laser pulses, each of which is less intensive than it is needed to cause the macroscopic breakdown. The problem under consideration includes both engineering and fundamental aspects. The practical interest is corresponded to the problem of long-term operation of optical elements in high-power laser systems. The main task of the theoretical analysis is to estimate the relative contribution of impurity-related and intrinsic processes into the phenomenon of `fatigue' (cumulative) damage. The experimental data concerning the subthreshold laser-induced damage are reviewed here, together with the proposed to date multi-shot damage mechanisms, which are described in the main features.

A two-dimensional simulation of organic transistors

Abstract: In this paper, we analyze the operation of organic thin-film transistors (TFT's) using two-dimensional (2-B) numerical simulation to: (1) validate the use of simple MOSFET theory to describe the above-threshold behavior; (2) clarify the subthreshold characteristics, and short-channel effects; and (3) illustrate the operation of organic bilayer devices. Our analysis clarifies a number of issues that can help in device design. We also point out differences between the material parameters used in Si-MOSFET and organic FET simulation, and discuss the circumstances under which a semiconductor device simulator can be used for the simulation of organic transistors.

Bistable biochemical switching and the control of the events of the cell cycle

Abstract: Some of the events of the cell cycle appear to be triggered by a bistable mechanism. A bistable biochemical system can respond to a small, slow signal and is carried by positive feedback from one stable steady state directly to another, in an all-or-none manner. Slow or subthreshold stimuli do not cause accommodation or loss of excitability. Switching is not readily reversible by removing the stimulus, i.e. there is hysteresis: reversal generally requires a stronger, opposite stimulus. Biochemically, bistable biochemical switching requires positive feedback, and mechanisms for stabilizing the system against premature activation and for destabilization in response to a biological signal. Three bistable bio-chemical models, all suggested by reported experimental observations, are described and analysed. These models suggest that a titratable inhibitor may play an important part in bistable switching, because the end-point of titration can form a natural threshold for enhancement of positive feedback.

Modeling of laser-annealed polysilicon TFT characteristics

Abstract: A model based on two-dimensional (2-D) simulation, for a polysilicon thin-film transistor (poly-Si TFT) with large grains, fabricated in laser recrystallized material, is presented. The importance of differentiating between the density of states of traps within grains and traps localized at grain boundaries is demonstrated. It is shown that the observed lack of saturation in the TFT output characteristics arises due to the effect of high interface trap density within the grain boundaries, whereas the subthreshold slope has a strong dependence on the trap density within the grains. Only by differentiating in this way between grain and grain boundary parameters can both output and subthreshold characteristics of an n-channel poly-Si TFT be accurately modeled using the same set of parameters. Appropriate values for the density of states in both grains and grain boundaries are suggested for laser-annealed TFTs.

A Complementary Pair of Four-Terminal Silicon Synapses

Abstract: We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01 percent The synapses are small, and typically are operated at subthreshold current levels; they will permit the development of dense, low-power silicon learning systems.

Si/SiGe MOSFET and method for fabricating the same

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistors are used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors, using the gate spacers in a conventional manner, and/or as conventional transistors.

Silicon Retina with Adaptive Filtering Properties

Abstract: This paper describes a small, compact circuit, the retino-laminar (RL) circuit, that captures the temporal and adaptation properties both of the photoreceptor and of the laminar layers of the fly. The RL circuit uses only six transistors and two capacitors. The circuit is operated in the subthreshold domain; it has a low DC gain and a high transient gain. The adaptation time constant of the RL circuit can be controlled via an external bias. Its temporal filtering properties change with the background intensity and with the signal-to-noise ratio. The frequency response of the circuit shows that, in the frequency range of 1 to 100 Hz, the circuit response goes from highpass filtering under high light levels to lowpass filtering under low light levels (i.e., when the signal-to-noise ratio is low).

Analysis, synthesis, and implementation of networks of multiple-input translinear elements

Abstract: At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steady-state relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steady-state transfer characteristics embody some desired product-of-power-law relationship between input and output currents. These circuits are made from multiple-input translinear elements; such elements produce output currents that are proportional to the exponential of a weighted sum of their input voltages. We can implement the weighted voltage summations with either resistive or capacitive voltage dividers. We can obtain the required exponential voltage-to-current transformations from either bipolar transistors or subthreshold MOS transistors. The subthreshold floating-gate MOS transistor naturally implements the exponential-of-a-weighted-sum operation in a single device. I will present experimental results from several of these translinear network circuits breadboarded from subthreshold floating-gate MOS transistors. I will also describe and present experimental data from a variety of other implementations of the multiple-input translinear element.

Semiconductor memory device with reduced leak current

Abstract: In a data holding mode, a potential on a substrate region in a memory cell array is fixed at the same level as that in a normal operation mode, and an absolute value of a bias voltage applied to a substrate region in a peripheral circuit is made larger than that in the normal operation mode. When an operation mode changes, a memory cell transistor substrate potential does not change, and therefore a potential on a storage node of a memory cell does not change, so that the storage data is stably held. A threshold voltage of an MOS transistor in the peripheral circuit increases in absolute value, and a subthreshold current is reduced. A current consumption is reduced in the data holding mode of a semiconductor memory device without adversely affecting storage data.

A differential built-in current sensor design for high-speed IDDQ testing

Abstract: A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. This differential design also naturally compensates for inaccuracies due to any build up of leakage currents and subthreshold conduction effects when relatively large circuit partitions are tested. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated. At clock speeds of up to 31.25 MHz the sensor accurately detects all six of the defects that were implanted in the test chip. SPICE3 simulations of the circuit indicate that with careful design, this sensor can accurately detect faults at operational speeds in a variety of situations.

Memory circuit including write control unit wherein subthreshold leakage may be reduced

Abstract: A memory circuit wherein subthreshold leakage current may be reduced. The memory circuit includes a memory array composed of one or more storage cells that are each configured to store a memory value on a storage transistor. The storage cells further include a write transistor coupled to the storage transistor that is configured to allow data driven on a write bit line to be stored to the storage transistor. The write bit line is coupled to a write control unit, which includes a buffer and a offset voltage element. The buffer is configured to establish an output voltage on the write bit line in response to an input voltage. The offset voltage element is coupled to the buffer, and is configured to offset the output voltage on the write bit line by a predetermined amount. In one implementation of the write control unit, the buffer is formed by an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a diode-connected transistor coupled between the inverter and ground. The diode-connected transistor has the effect of holding the write bit line at a level equal to its threshold voltage when the n-channel transistor of the inverter is active. In another implementation, the buffer is also an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a pullup transistor that is active when the n-channel transitor of the inverter is active. The pullup transistor forms a voltage divider with the n-channel transistor, such that the voltage between the write bit line and ground is offset by an amount determined by the voltage drop across the pullup transistor. The offset voltage established by the write control unit biases the write transistor such that subthreshold leakage current may be reduced when the write transistor is off.

A new empirical large signal model for silicon RF LDMOS FETs

Abstract: A new empirical large signal drain current source model, that is single-piece and continuously differentiable, has been developed for silicon LDMOS transistors. The new model is capable of accurately representing the current-voltage characteristics and their derivatives. A single continuously differentiable form models the subthreshold, triode, and saturation regions of operation. The model was implemented in a commercial harmonic balance simulator and parameter extraction software. Measured and simulated load-pull results at a class AB operating point are compared and show very good agreement.

Modeling the subthreshold swing in MOSFET's

Abstract: This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current.

Hole impact ionization mechanism of hot electron injection and four-terminal ρFET semiconductor structure for long-term learning

Abstract: Hot-electron injection driven by a hole impact ionization mechanism at the channel-drain junction provides a new method of hot electron injection. Using this mechanism, a four-terminal pFET floating-gate silicon MOS transistor for analog learning applications provides nonvolatile memory storage. Electron tunneling permits bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. The synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. Synaptic arrays employing these devices enjoy write and erase isolation between array synapses is better than 0.01% because the tunneling and injection processes are exponential in the transistor terminal voltages. The synapses are small, and typically are operated at subthreshold current levels.

Fuzzy logic architecture using subthreshold analogue floating-gate devices

Abstract: A subthreshold fuzzy logic architecture is proposed which includes floating-gate devices acting as nonvolatile analogue memories. The use of floating-gate devices which are embedded within the architecture reduces the size and power consumption of the system. Using the proposed subcircuits, a system containing 75 rules can be implemented in less than 5 mm/sup 2/ while consuming 500 /spl mu/W. The system is, therefore, suitable for integration within a smart sensor, an application area in which low-power consumption and compactness are potentially critical.

Subthreshold analysis of an MOS analog switch

Abstract: Charge injection error in the presence of subthreshold effects has been analyzed. It is confirmed that the subthreshold effect is significant at low voltage falling rates. A simplified model is derived using an appropriate approximation. Predictions are compared to the results of a SPICE simulation, a nonquasi-static (NQS) model simulation and experimental results. Excellent agreement between the modified and NQS model and recently published experimental results was obtained. This analytical model is computationally efficient compared to the SPICE and NQS models and provides physical insight into the switching errors.

Method of programming and/or verifying a threshold voltage level of a nonvolatile memory cell

Abstract: A method of at least one of programming and verifying a threshold voltage of a nonvolatile memory cell. The memory cell includes a control gate, a floating gate, a drain, a source, and a channel region between the drain and the source. The method is a voltage-type programming compared to a current type programming. A first voltage, which varies in correspondence to each threshold level programming, is applied to the control gate, and second and third voltages are applied to the drain and the source, respectively, so that the channel region is turned off at an initial stage and charge carriers for the programming are transferred from the floating gate to the drain. A conductivity of the channel region is monitored during each threshold level programming. The application of at least one voltage among the first voltage, second voltage and third voltage is cut-off to stop the programming when the monitored conductivity reaches a reference value which may be constant for every threshold level to be programmed and/or verified.

Matrix-assisted Laser Desorption/Ionization by Two Collinear Subthreshold Laser Pulses

Abstract: Two nitrogen laser pulses of subthreshold irradiance were used to achieve matrix-assisted laser desorption/ionization in a collinear configuration. Optimum laser pulse delay times yielding maximum guest ion intensities were determined for four different matrices between 4.2 ns for sinapinic acid (SA) and 12.5 ns for 2,5-dihydroxybenzoic acid (DHB). The signal decay times followed an opposite trend to the position of maxima, DHB being the fastest decaying (1.1 ns) and SA the slowest (9.8 ns). Collinear subthreshold experiments allow for a two orders of magnitude improvement in spatial and time resolution over post-ionization experiments. © 1997 by John Wiley & Sons, Ltd.