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Showing papers on "Subthreshold conduction published in 1998"


Journal ArticleDOI
31 Aug 1998-Chaos
TL;DR: It is suggested that an electrical noise-based technique could be used to improve tactile sensation in humans when the mechanical stimulus is around or below threshold, and input electrical noise can serve as a negative masker for subthreshold mechanical tactile stimuli.
Abstract: Stochastic resonance (SR) is a phenomenon wherein the response of a nonlinear system to a weak input signal is optimized by the presence of a particular, nonzero level of noise. Our objective was to demonstrate cross-modality SR in human sensory perception. Specifically, we were interested in testing the hypothesis that the ability of an individual to detect a subthreshold mechanical cutaneous stimulus can be significantly enhanced by introducing a particular level of electrical noise. Psychophysical experiments were performed on 11 healthy subjects. The protocol consisted of the presentation of: (a) a subthreshold mechanical stimulus plus electrical noise, or (b) no mechanical stimulus plus electrical noise. The intensity of the electrical noise was varied between trials. Each subject’s ability to identify correctly the presence of the mechanical stimulus was determined as a function of the noise intensity. In 9 of the 11 subjects, the introduction of a particular level of electrical noise significantly enhanced the subject’s ability to detect the subthreshold mechanical cutaneous stimulus. In 2 of the 11 subjects, the introduction of electrical noise did not significantly change the subject’s ability to detect the mechanical stimulus. These findings indicate that input electrical noise can serve as a negative masker for subthreshold mechanical tactile stimuli, i.e., electrical noise can increase the detectability of weak mechanical signals. Thus, for SR-type effects to be observed in human sensory perception, the noise and stimulus need not be of the same modality. From a bioengineering and clinical standpoint, this work suggests that an electrical noise-based technique could be used to improve tactile sensation in humans when the mechanical stimulus is around or below threshold.

129 citations


Journal ArticleDOI
TL;DR: In this article, the power spectral densities of the gate voltage and drain current were investigated under various bias conditions ranging from subthreshold to saturation, and it was found that it is advisable to limit the bias voltages to values that are experimentally determined from the transconductance characteristics and correspond to a nearly constant channel mobility.
Abstract: Detailed noise measurements of the 1/ f noise in p - and n -mos transistors for analog applications are reported under various bias conditions ranging from subthreshold to saturation. The CMOS transistors under study have a relatively large area, exhibit long channel behavior and are fabricated in a commercial “low noise process”, as prescribed for analog applications. A clear methodology and useful models for the power spectral densities of the gate voltage and drain current are presented and are based on recent studies in sub-micron transistors that have established the physical origin of 1/ f noise in MOS transistors. In saturation, it is found that it is advisable to limit the bias voltages to values that are experimentally determined from the transconductance characteristics and correspond to a nearly constant channel mobility. The experimentally observed reduction in channel mobility indicates the existence of strong fields that induce additional oxide charging and hence an increase in the effective density of oxide traps and the noise. In the bias voltages where channel mobility is nearly constant, the measured input-referred noise power is practically constant. Below threshold voltage, a reduction is observed in the input-referred noise as gate voltage is decreased, corresponding to the prediction of the model and due to the exponential reduction of the inversion capacitance with gate voltage. This behavior is observed for both n -mos and p -mos transistors.

116 citations


Journal ArticleDOI
TL;DR: In this paper, the authors proposed a threshold voltage model for surrounding-gate MOSFETs, which treats the ends and the double-gate regions of the channel as separate devices operating in parallel.
Abstract: We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner.

72 citations


Proceedings ArticleDOI
Kaushik Roy1
07 Sep 1998
TL;DR: In this article, the authors present different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.
Abstract: Lowering supply voltage is one of the most effective ways of reducing power dissipation. Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between the leakage current and the transistor threshold voltage in the weak inversion region, static current (and hence, static power power dissipation) can no longer be ignored. In this paper the author presents different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.

64 citations


Patent
Kiyoo Itoh1, Hiroyuki Mizuno1
20 Feb 1998
TL;DR: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off as mentioned in this paper.
Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

53 citations


Journal ArticleDOI
TL;DR: Analysis of the transmembrane voltage response of an unmyelinated fiber to a stimulating electric field from a point current source finds that the subthreshold response is a good predictor of the wave shape of the suprathreshold vm, but a poor predictor of its magnitude.
Abstract: The authors consider the determination of conditions when an excitable membrane can be considered linear and steady-state. The following topics are dealt with: threshold for a space-clamped fiber; threshold for a fiber stimulated by a point current source; subthreshold response; passive vs. active response; defibrillation stimulus-response time-constant; the transient intracellular current; the transient transmembrane potential due to junctional resistance.

50 citations


Patent
24 Feb 1998
TL;DR: In this paper, a bias potential of a substrate is adjusted according to the comparison result to hold the sub-threshold current at the reference current to compensate for process, activity and temperature-induced device threshold variations in a semiconductor circuit.
Abstract: To compensate for process, activity and temperature-induced device threshold variations in a semiconductor circuit having a transistor, a potential of the gate the transistor is held to a preset subthreshold potential, and a channel current of the channel region is compared with a reference current to obtain a comparison result. A bias potential of a substrate is adjusted according to the comparison result to hold the subthreshold current at the reference current.

46 citations


Journal ArticleDOI
TL;DR: In this article, a drain current model for surrounding gate MOSFETs was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation.
Abstract: In this paper we present a complete and analytical drain current model for surrounding gate MOSFETs. The model was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; single-piece drain current equation smoothly continuous from the linear region to the saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain-induced barrier lowering and channel length modulation.

40 citations


Patent
23 Jan 1998
TL;DR: In this paper, a master cell is configured to regulate the bias voltage precisely over a wide range of load currents from the slave cells, thus eliminating the need for a current boosting voltage follower between the master cell and each slave cell.
Abstract: Methods and circuits for biasing a transconducting cell to operate in a subthreshold state so as to have a desired high transconductance, and systems including a master cell for generating a regulated bias voltage and one or more transconducting slave cells biased in subthreshold by the bias voltage. An example of such system is an inverting voltage amplifier (offering low power consumption, low noise, good stability, and high gain). The bias voltage is generated to be independent of process and environmental variations by servoing an unregulated supply voltage, and preferably has lower magnitude relative to ground than the supply voltage. Preferably, the master cell includes transistors in which a constant current density is maintained, and this current density is replicated in each slave cell biased by the master cell. Preferably, the master cell is configured to regulate the bias voltage precisely over a wide range of load currents from the slave cells, thus eliminating the need for a current boosting voltage follower between the master cell and each slave cell. The slave cell can comprise multiple transconducting stages (each biased in subthreshold), an integrator having multiple inverter stages (and at least one feedback stage providing displacement current to one of the stages), cascoded transistor pairs, or an NMOS transistor and PMOS transistor biased in subthreshold with gate potentials offset by different amounts above and below an input voltage.

40 citations


Journal ArticleDOI
TL;DR: In this paper, the drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT.
Abstract: The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT. Each of the three shows different dependencies on back-gate bias. As a result, the bulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage. Additional experiment highlights the effect of the increased bulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT. This sets the bulk BTBT a significant constraint to the low-voltage, low-power, high-density CMOS integrated circuits employing the back-gate reverse bias. In this work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation.

38 citations


Proceedings ArticleDOI
13 Sep 1998
TL;DR: In this paper, a transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced, which describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of carrier velocity saturation, vertical and lateral high field mobility degradation, and threshold voltage roll-off.
Abstract: A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P/sub SC/), and 3) static power (P/sub Static/). Results from the total power (P/sub Total/) consumption analysis indicate that P/sub SC/ and P/sub Static/ may constitute over 1/3 of P/sub Total/ in future low power/high performance CMOS GSI.

Proceedings ArticleDOI
19 Oct 1998
TL;DR: In this article, the authors present simulation results for the subthreshold characteristics of n-channel MOSFETs with 0.1 /spl mu/m gate-length and 0.05 /spl m/m buffer-width obtained with their 3D-DD simulator.
Abstract: The authors present simulation results for the subthreshold characteristics of n-channel MOSFETs with 0.1 /spl mu/m gate-length and 0.05 /spl mu/m gate-width obtained with our 3D-DD simulator. We also presented a new method that one can successfully use in a particle-based simulator to properly account for the short-range portions of the e-e and e-i interactions without double-counting the long-range portions of these two interaction terms.

Journal ArticleDOI
TL;DR: It is demonstrated that a noisy Hodgkin/Huxley-model for subthreshold oscillations, when tuned to maximum sensitivity, can be significantly modulated by even minor physiological changes in the oscillation parameters amplitude or frequency.
Abstract: Intrinsic subthreshold oscillations in the membrane potential are a common property of many neurons in the peripheral and central nervous system. When such oscillations are combined with noise, interesting signal encoding and neuromodulatory properties are obtained which allow, for example, sensitivity adjustment or differential encoding of stimuli. Here we demonstrate that a noisy Hodgkin/Huxley-model for subthreshold oscillations, when tuned to maximum sensitivity, can be significantly modulated by even minor physiological changes in the oscillation parameters amplitude or frequency. Given the ubiquity of subthreshold oscillating neurons, it can be assumed that these findings reflect principle encoding properties which are relevant for an understanding of sensitivity and neuromodulation in peripheral and central neurons.

Proceedings ArticleDOI
07 Sep 1998
TL;DR: The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay, and it has been shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and anIC with long L, with low P/ sub LEAK/, will be slower.
Abstract: A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to process is introduced. Using these models, the P/sub LEAK/ distribution is found to be asymmetric around the nominal value showing a long tail for high consuming circuits. The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay. We have shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and an IC with long L, and therefore, with low P/sub LEAK/ will be slower. Predicted results are consistent with available experimental data.

Journal ArticleDOI
TL;DR: In this paper, an Ultra Low Noise CMOS charge-sensitive amplifier (CSA) and a CSA-shaper for X-ray spectroscopy was proposed. But the performance of the CSA was not evaluated.
Abstract: We report here an Ultra Low Noise CMOS charge-sensitive amplifier (CSA) and a CSA-Shaper for X-ray spectroscopy, suitable for a small anode capacitance, low leakage current solid state detector. The continuously sensitive CSA and CSA-Shaper use a MOS transistor MF to discharge the integration capacitance; a novel self-bias circuit biases MF in the GΩ region (subthreshold region) while tracking process, temperature and supply voltage variations. A T-Network in the DC-feedback improves the CSA gain linearity (within 0.1% up to 1.8 fC input charge). The CSA-Shaper features a novel Adaptive Pole-Zero cancellation scheme: the Zero in the Shaper adapts itself statically and dynamically to cancel the CSA Pole. The noise performance of the CSA has been measured: with no detector connected and MF pinched, the room-temperature equivalent noise charge (ENC) is 9e rms at 12 μs shaping time. When connected to a cooled detector (T=−75°C), with MF in pinch off, an ENC of 13e rms is achieved (FHWM=111 eV) at 2.4 μs shaping time. This is the best reported energy resolution ever obtained with a CMOS preamplifier.

Journal ArticleDOI
TL;DR: A simple and accurate MOSFET channel charge model for device modeling in circuit simulation that agrees with the experimental data well at various process and bias conditions from subthreshold and strong inversion, including the moderate inversion region of growing importance for low-voltage/power circuits.
Abstract: In this paper, we present a simple and accurate MOSFET channel charge model for device modeling in circuit simulation. The model can guarantee good continuities and smooth transitions of charge, capacitance, current, and transconductance from subthreshold to strong inversion with a unified analytical expression, and agrees with the experimental data well at various process and bias conditions from subthreshold and strong inversion, including the moderate inversion region of growing importance for low-voltage/power circuits.

Journal ArticleDOI
TL;DR: In this paper, measurements on submicron metal-oxide-semiconductor field effect transistors equipped with a gate on three sides of the channel were performed at room temperature and liquid helium temperatures.
Abstract: We report measurements on submicron metal–oxide–semiconductor field effect transistors equipped with a gate on three sides of the channel. At room temperature, a strong suppression of short-channel effects has been achieved for the narrowest channels. At liquid helium temperatures, the same devices exhibit clear conductance oscillations in the subthreshold regime, indicating that a quantum dot has formed in the disordered channel.

Patent
13 Aug 1998
TL;DR: In this paper, the DRAM memory unit is tested for a series of cell faults such as stuck-at fault (SAF), stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) as well as storage capacitor leakage, subthreshold leakage or junction leakage.
Abstract: DRAM memory unit is tested for a series of cell faults such as: the stuck-at fault (SAF), the stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) as well as storage capacitor leakage, subthreshold leakage or junction leakage. Predetermined data pattern is written throughout the DRAM memory, locations in one region of the memory are “frozen” while a disturbance is created in a second region during an interval sufficient for a defective cell in the first region to lose its charge, following which the locations of the first region are sequentially read to verify if any cell has lost its data.

Journal ArticleDOI
TL;DR: In this paper, an anomalous sub-threshold characteristic of the MOSFET for lowvoltage operation was reported, and the cause of channel length independent subthreshold characteristics was identified as the localized pileup of channel dopants near the source and drain ends of the channel.
Abstract: This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation.

Proceedings ArticleDOI
09 Jun 1998
TL;DR: In this article, the dependence of dopant-induced V/sub TH/ fluctuation was analyzed using a newly proposed quasi-resistance method and it was revealed that the (LW)/sup -1/2/ relationship originates from a V/ sub TH/ averaging effect, caused by the subthreshold current.
Abstract: L and W dependence of dopant-induced V/sub TH/ fluctuation is analyzed using a newly proposed quasi-resistance method. It is revealed that the (LW)/sup -1/2/ relationship originates from a V/sub TH/ averaging effect, caused by the subthreshold current. The relationship is expected to hold down to 0.1 /spl mu/m generation.

Patent
Hideaki Nagaoka1
30 Jan 1998
TL;DR: In this article, an MOS transistor having a low threshold voltage and a standard MOS transistors having threshold voltages of large absolute values are connected in series between an output node and a power supply node.
Abstract: In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor. A gate circuit having a small dependency of an input/output characteristics on the power supply voltage is implemented without increasing the power consumption.

Journal ArticleDOI
TL;DR: An active membrane model that included a subthreshold A-type K+ current and/or a hyperpolarization-activated cation current (H-current) then was used to model cell behavior and the voltage traces calculated using this model were better able to reproduce the experimental data, and the cable parameters determined using this methodology were more consistent with those reported for other cells.
Abstract: Surkis, A., C. S. Peskin, D. Tranchina, and C. S. Leonard. Recovery of cable properties through active and passive modeling of subthreshold membrane responses from laterodorsal tegmental neurons. J...

Journal ArticleDOI
Hoi-Jun Yoo1
TL;DR: In this article, a sub-threshold current reduction logic, DVST, was proposed for the possible application to multigigabit synchronous DRAM, which can operate two times faster than the conventional dual-V/sub T/ logic at 1.0-V supply voltage.
Abstract: A subthreshold current reduction logic, the dual-V/sub T/ self-timed (DVST) logic, is developed for the possible application to multigigabit synchronous DRAM. Minimizing subthreshold current is a critical problem in low-voltage CMOS logic. DVST logic has potential advantages over conventional dual-V/sub T/ logic in terms of circuit delay, subthreshold current, operating voltage, and area consumption. A detailed comparison of the conventional logic and the DVST logic is carried out by SPICE simulation. Methods for the determination of the threshold voltages of low-and high-V/sub T/ MOS transistors, for the optimization of the width of the MOS transistors in the circuit, and for the determination of the delay time of the resetting signal are developed. Examples of basic logic blocks and inverter chains are illustrated with their simulation results. The DVST logic circuit in which the subthreshold leakage current path is blocked by a large high-V/sub T/ MOS transistor can reduce the subthreshold current to the same level of high-V/sub T/ logic. It can operate two times faster than the conventional dual-V/sub T/ logic at 1.0-V supply voltage by removing the limitation in /spl gamma/ of the dual-V/sub T/ logic. In the voltage range of 0.8-1.5 V it operates at even higher speed than the low-V/sub T/ logic and only below 0.7-V supply voltage it is exceeded by the low-V/sub T/ logic. Its application to synchronous DRAM, especially in the wave pipeline architecture of the data path, is described.

Journal ArticleDOI
TL;DR: In this article, the bias independent 1/f noise spectrum of the n-channel TFSOI MOSFET was investigated in the subthreshold region, linear region, and saturation region of operation for the first time.
Abstract: Low-frequency (1/f) noise in near-fully-depleted Thin-Film Silicon-On-Insulator (TFSOI) CMOS transistors designed for sub-l-V applications is investigated in the subthreshold region, linear region, and saturation region of operation for the first time. The noise in these surface-channel devices is composed of a bias invariant 1/f component and a bias dependent generation-recombination (G/R) component that becomes enhanced in the subthreshold region of operation for both n- and p-channel MOSFETs. Results presented in this letter are consistent with the noise being dominated by a number fluctuation model. These results demonstrate that the bias independent 1/f noise spectrum of the n-channel TFSOI MOSFET is comparable to the 1/f noise level found in conventional bulk silicon submicron CMOS fabrication processes.


Patent
23 Jan 1998
TL;DR: In this paper, the bias voltage is generated by servoing an unregulated supply voltage so that the voltage has lower magnitude (relative to ground potential) than the supply voltage, thereby causing the cell to operate in sub-threshold.
Abstract: A comparator including one or more transconducting inverters, each inverter biased to operate in a subthreshold state so as to have a desired high transconductance. In preferred embodiments, the transconducting inverter is biased in subthreshold by a bias voltage whose value is independent of process and environmental variations (so that the subthreshold current density in the inverter remains fixed despite supply voltage variations and other process and environmental variations). The bias voltage is generated by servoing an unregulated supply voltage so that the bias voltage has lower magnitude (relative to ground potential) than the supply voltage. The reduced-magnitude, regulated bias voltage precisely regulates at least one transistor in each inverter by forcing a constant current density therein, thereby causing the cell to operate in subthreshold. Due to the process-independent nature of the closed loop servo system inherent in the bias voltage generation circuitry, the bias voltage can be reliably generated with a precise, desired value which forces subthreshold operation of each inverter, and this precise bias voltage can be reliably distributed to multiple inverter. Also within the scope of the invention are analog-to-digital conversion circuits, each including a slave cell implemented as a CMOS inverter and biased in accordance with the invention, and switching circuitry implemented with CMOS technology (or with NMOS transistors but without PMOS transistors).

Journal ArticleDOI
TL;DR: In this article, the subthreshold current activation energy in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) is compared for n-channel nonpassivated TFT devices before and after bias stress.
Abstract: Both the subthreshold slope and the threshold voltage in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) are vulnerable to metastable changes in the density of states (DOS) due to Fermi level displacement. In previous work, we have used passivated and unpassivated TFTs to distinguish between the effects of bulk states and interface states at the top passivating nitride interface. Here we report the results of experimental measurements and two-dimensional (2-D) simulations on unpassivated TFTs. Since there are no top interface states, all the observed changes are due solely to the bulk DOS. The subthreshold current activation energies in a-Si:H TFTs are compared for n-channel nonpassivated TFTs before and after bias stress. The experimental results agree well with the 2-D simulations, confirming that the dependence of subthreshold current activation energy on gate bias reveals the distribution of the DOS in energy but cannot resolve the magnitude of features in the DOS. This type of analysis is not accurate for TFTs with a top passivating nitride, since the activation energies in such devices are affected by the interfere states.

Patent
06 Apr 1998
TL;DR: In this article, a subthreshold conduction current compensation circuit was proposed to reduce undesired effects of sub-threshold current in a first field effect transistor (FET) during the holding time.
Abstract: An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor. A unity gain buffer amplifier may be connected to the body of the first FET during the holding time for applying a holding voltage from the sampling capacitor to the body to thereby reduce undesired effects from the parasitic diode. The subthreshold current conduction compensation circuit causes a voltage at the first conduction terminal of the first FET to be substantially equal to a voltage at the second conduction terminal of the first FET during the holding time. This may be accomplished by coupling the holding voltage from the output of the buffer amplifier to the node between two series connected FETs.

Journal ArticleDOI
TL;DR: In this paper, the electrical characteristics of proton-implanted GaAs quantum-well vertical-cavity surface-emitting semiconductor lasers (VCSELs) have been studied and the contribution of these mechanisms to the total nonradiative current and threshold current density has been calculated.
Abstract: The electrical characteristics of proton-implanted GaAs quantum-well vertical-cavity surface-emitting semiconductor lasers (VCSELs) have been studied. We show that the 2 kT current, observed over many decades in these VCSELs, is primarily due to nonradiative recombination mechanisms. These include surface recombination at the edges of the proton-implanted region and bulk recombination at defects and heterojunction interface traps. The contribution of these mechanisms to the total nonradiative current and the threshold current density has been calculated. Lateral spontaneous emission measurements have been used to prove that the radiative current has a kT behavior in the subthreshold region. Electrical derivative measurements have been used to identify leakage current paths through the proton-implanted region in the low-bias regions. In addition, electrical derivative measurements have been used to measure the variation of series resistance with current near the lasing threshold. From a consideration of the various current paths in the VCSEL, a lumped circuit equivalent model for the VCSEL has been developed.

01 Jan 1998
TL;DR: In this paper, the dependence of dopant-induced VTH fluctuation was analyzed using a newly proposed quasi-resistance method and it was revealed that the (Lw)-'n relationship originates from a VTH averaging effect, caused by the subthreshold current.
Abstract: L and W dependence of dopant-induced VTH fluctuation is analyzed using a newly proposed quasi-resistance method. It is revealed that the (Lw)-'n relationship originates from a VTH averaging effect, caused by the subthreshold current. The relationship is expected to hold down to 0.1 pm generation.