Showing papers on "Subthreshold conduction published in 1999"

Control of action potential timing by intrinsic subthreshold oscillations in olfactory bulb output neurons.

Abstract: Rhythmic patterns of neuronal activity have been found at multiple levels of various sensory systems. In the olfactory bulb or the antennal lobe, oscillatory activity exhibits a broad range of frequencies and has been proposed to encode sensory information. However, the neural mechanisms underlying these oscillations are unknown. Bulbar oscillations might be an emergent network property arising from neuronal interactions and/or resulting from intrinsic oscillations in individual neurons. Here we show that mitral cells (output neurons of the olfactory bulb) display subthreshold oscillations of their membrane potential. These oscillations are mediated by tetrodotoxin-sensitive sodium currents and range in frequency from 10 to 50 Hz as a function of resting membrane potential. Because the voltage dependency of oscillation frequency was found to be similar to that for action potential generation, we studied how subthreshold oscillations could influence the timing of action potentials elicited by synaptic inputs. Indeed, we found that subthreshold oscillatory activity can trigger the precise occurrence of action potentials generated in response to EPSPs. Furthermore, IPSPs were found to set the phase of subthreshold oscillations and can lead to "rebound" spikes with a constant latency. Because intrinsic oscillations of membrane potential enable very precise temporal control of neuronal firing, we propose that these oscillations provide an effective means to synchronize mitral cell subpopulations during the processing of olfactory information.

Electrophoretic displays and systems for addressing such displays

Abstract: Electrophoretic displays include a light-emitting layer, a photoconductive layer, and an electrophoretic layer. The light-emitting layer may be an organic, light-emitting material, or organic, light-emitting diode, which is addressable using a multiplex addressing drive scheme. The impedance of the photoconductive layer is lowered when struck by light from the light-emitting layer. As a result of the lowered impedance of the photoconductive layer, the electrophoretic layer, which itself cannot be multiplexed, is addressed at a lower, subthreshold voltage.

A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

Abstract: In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 /spl mu/m. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort.

Ultra-low power digital subthreshold logic circuits

Abstract: Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.

Connection between asymptotic normalization coefficients, subthreshold bound states, and resonances

Abstract: We present here useful relations showing the connection between the asymptotic normalization coefficient (ANC) and the fitting parameters in K- and R-matrix theory methods which are often used when analyzing low energy experimental data. It is shown that the ANC of a subthreshold bound state defines the normalization of both direct radiative capture leading to this state and resonance capture in which the state behaves like a subthreshold resonance. A determination of the appropriate ANC(s) thus offers an alternative method for finding the strength of these types of capture reactions, both of which are important in nuclear astrophysics.

A physical alpha-power law MOSFET model

Abstract: A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original alpha-power law model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current tradeoff that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to the National Technology Roadmap for Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration.

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Abstract: The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits With the supply voltage at 1 V and threshold voltage as low as 02 V the subthreshold leakage power of transistors starts dominating the dynamic power Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 2945% Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when an arbitrary number of threshold voltages are allowed

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

Abstract: A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

Abstract: We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology. We also show: (1) the optimum reverse body bias value reduces by /spl sim/2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by /spl sim/4X per generation under constant field technology scaling scenario. Optimum point occurs as a result of reduction in subthreshold leakage and an increase injunction band-to-band tunneling leakage with applied reverse bias. Therefore, new junction engineering techniques to reduce the bulk band-to-band tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

A general translinear principle for subthreshold MOS transistors

Abstract: This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear principle applies immediately as long as the source-to-bulk voltages are made equal to zero (or constant). This paper addresses the conditions under which subthreshold MOS transistors still satisfy a translinear principle, but without imposing this constraint on all V/sub BS/ voltages. It is found that the translinear principle results in a more general formulation than the originally found for BJT's since now multiple translinear loops can be involved. The constraint of an even number of transistors is no longer necessary. Some corollaries are stated as well and, finally, it is shown how to use the theorem for subthreshold MOS transistors operated in the ohmic regime.

A physical alpha-power law MOSFET model

Abstract: A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: (1) a subthreshold region of operation for evaluating the on/off current trade-off that becomes a dominant low power design issue as technology scales, (2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and (3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to NTRS extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration (GSI).

Technology and design challenges for low power and high performance [microprocessors]

Abstract: We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks and interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

Detailed investigation of n-channel enhancement 6H-SiC MOSFETs

Abstract: Basic MOSFET parameters like inversion layer mobility, threshold voltage, intrinsic mobility reduction factor and interface state density extracted from the subthreshold slope were examined in detail for 6H-SiC enhancement-mode n-channel MOSFETs. The inversion layer mobility and the threshold voltage were determined as a function of substrate doping concentration as well as device temperature. The interface state density was studied for different substrate doping concentrations. The inversion layer mobility was found to decrease strongly with increasing substrate doping. In contrast to earlier reports the inversion layer mobility decreases also with temperature. Furthermore, the threshold voltage depends more pronounced on substrate doping and temperature than theoretically expected. The interface state density extracted from the subthreshold slope increases significantly with substrate doping concentration. All these phenomena are consistently interpreted by the classical MOSFET behavior which is extended by acceptor like interface states. These states are located close to the conduction band and exhibit a density increasing drastically toward the band edge.

Maximum leakage power estimation for CMOS circuits

Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. As the device threshold voltage is reduced, it results in an exponential increase of leakage current in the subthreshold region. The leakage power is no longer negligible in such low voltage circuits. Estimates of maximum leakage power can be used in the design of the circuit to minimize the leakage power. The leakage power is dependent on the input vector. This input pattern dependence of the leakage power makes the problem of estimating the maximum leakage power a hard problem. In this paper, we present graph based algorithms for estimating the maximum leakage power. These algorithms are pattern-independent and do not require simulation of the circuit. Instead the circuit structure and the logic functionality of the components in the circuit are used to create a constraint graph. The problem of estimating the maximum leakage power is then transformed to an optimization problem on the constraint graph. Efficient algorithms on the graph are used to estimate the maximum leakage power dissipated by a circuit. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

1/f noise in ion sensitive field effect transistors from subthreshold to saturation

Abstract: The present paper presents extensive measurements of low frequency noise in pH ion sensitive field effect transistors (ISFET's) under various bias conditions corresponding to the gate voltage changing from subthreshold to saturation, in the frequency range between 1 Hz and 100 kHz. The noise measurements were performed in solutions with pH in the range of pH4 to pH10, at room temperature. In contrast to previously reported results, the measured ISFET's exhibit clearly 1/f noise down to 1 Hz.

Two-dimensional doping profile characterization of MOSFETs by inverse modeling using I-V characteristics in the subthreshold region

Abstract: In this paper, we present a new technique for the characterization of two-dimensional (2-D) doping profiles in deep submicron MOSFETs using current-voltage (I-V) characteristics in the subthreshold region. The main advantages of the technique are as follows. (1) It is capable of extracting 2-D doping profile (including channel-length) of deep submicron devices because of its immunity to parasitic resistance, capacitance, noise, and fringing electric fields. (2) It does not require any special test structures since only subthreshold I-V data are used. (3) It is nondestructive. (4) It has very little dependence on mobility and mobility models. (5) It is easy to use since data collection and preparation are straightforward. (6) It can be extended to the accurate calibration of mobility and mobility models using I-V characteristics at high current levels, because errors associated with uncertainties in doping profiles are removed.

Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices

Abstract: Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L/sub gate/ and the same off-state leakage current I/sub off/, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar.

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs

Abstract: The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V/sub gs/ such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 /spl Aring/) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 /spl Aring/) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.

On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs

Abstract: The subthreshold operation (subthreshold swing and leakage current) and the short channel effects (DIBL and charge sharing) are investigated in partially and fully depleted deep submicron N-channel SOI-MOSFETs by numerical simulation and experimental results. The use of lightly doped ultra-thin silicon films in single gate SOI-MOSFETs is shown to substantially improve the overall electrical properties. Furthermore, a double gate control in thin film SOI-MOSFETs leads to an ideal subthreshold swing together with optimum short channel effects and a reduced dependence on doping, Si layer thickness and drain bias.

Novel method for silicon quantum wire transistor fabrication

Abstract: Local stress-limited oxidation was used to fabricate silicon quantum wire transistors with a channel diameter of 5 nm. The oxidation of source and drain regions was prevented with a silicon nitride diffusion barrier. A novel wraparound gate was used to improve the gate control of the potential in the channel. The electrical properties of these devices were investigated at room temperature. Ideal subthreshold behavior, with the subthreshold swing equal to 60.3 mV/dec, was observed.

A transistor-only circuit model of the autozeroing floating-gate amplifier

Abstract: We developed an transistor-only version of our autozeroing floating-gate amplifier (AFGA). We use a subthreshold transistor to model the behavior of an electron-tunneling device, and we use another subthreshold transistor to model the behavior of pFET hot-electron injection. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data. This circuit is a bandpass filter, and behaves similarly to the AFGA with different operating parameters. Both the low-frequency and high-frequency cutoffs are controlled electronically, as is done in continuous-time filters. This circuit has a low-frequency cutoff at frequencies above 1 Hz, and therefore complements the operating regimes of the AFGA.

Modeling of threshold voltage and subthreshold swing of short-channel SOI MESFET's

Abstract: Short-channel effects on the subthreshold behavior are modeled for fully depleted Si-SOI MESFETs through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant minimum bottom potential caused by drain-induced barrier lowering, accurate analytical expressions for short-channel threshold voltage and subthreshold swing are derived. This model is verified by comparison to a two-dimensional device simulator, MEDICI, over a wide range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.2 μm.

Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation

Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.

Subthreshold and near-threshold K+-meson production on light nuclei by protons

Abstract: Inclusive K+-meson production in proton-nucleus collisions in the near-threshold and subthreshold energy regimes is analyzed with respect to the one-step (pN → K+YN, Y=Λ, Σ) and two-step (pN → NNπ, NN2π; πN → K+Y) incoherent production processes An appropriate folding model is used that properly takes into account the struck-target-nucleon-removal energy and the momentum distribution (nucleon spectral function), novel elementary cross sections for proton-nucleon reaction channel close to threshold, as well as nuclear-mean-field-potential effects on the one-step and two-step kaon-creation processes A detailed comparison of the model calculations of the K+ total and differential cross sections for the p+9Be and p+12C interactions with the existing experimental data is given, which displays both the relative role of the primary and secondary production channels at considered incident energies and those features of the cross sections that are sensitive to the high-momentum and high-removal-energy parts of the nucleon spectral function It is found that, contrary to previous studies known in the literature, the pion-nucleon production channels do not necessarily dominate in pA collisions at subthreshold energies and that the relative strength of the proton-and pion-induced reaction channels for light target nuclei in the subthreshold energy regime is governed by the kinematics of the experiment under consideration

Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFETs

Abstract: Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage.

Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits

Abstract: We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous, analytical expression for all regimes of operation, thereby improving convergence. The physics-based model includes effects such as velocity saturation in the channel, drain-induced barrier lowering (DIBL), finite output conductance in saturation, frequency dispersion, and temperature dependence. The output resistance and the transconductance are accurately reproduced, making the model suitable for simulation of mixed mode (digital/analog) circuits. The model has been extensively verified against experimental data for two HFET technologies with gate lengths down to 0.3 /spl mu/m.

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers

Abstract: This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V/sub th/) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V/sub th/ MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V/sub th/ MOSFETs, which are cut off during standby. The high-V/sub th/, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words/spl times/16-bits SRAM test chip, which was fabricated with a 0.5-/spl mu/m multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 /spl mu/W, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads.