Showing papers on "Subthreshold conduction published in 2000"

Dual-threshold voltage techniques for low-power digital circuits

Abstract: Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

Suprathreshold stochastic resonance in multilevel threshold systems

Abstract: A new form of stochastic resonance (SR) that occurs in multilevel threshold signal detectors is reported. In contrast to classical SR, which extends the dynamic range of threshold detectors to subthreshold signal levels, this new form of SR extends the dynamic range to suprathreshold signal strengths. The effect is most dominant, and can outperform networks based on standard engineering design, when all thresholds adapt to the dc level of the signal. This has an interesting analogy to dc adaptation in neurons. The possible connection between these two effects is discussed.

Noise in Integrate-and-Fire Neurons: From Stochastic Input to Escape Rates

Abstract: We analyze the effect of noise in integrate-and-fire neurons driven by time-dependent input and compare the diffusion approximation for the membrane potential to escape noise. It is shown that for time-dependent subthreshold input, diffusive noise can be replaced by escape noise with a hazard function that has a gaussian dependence on the distance between the (noise-free) membrane voltage and threshold. The approximation is improved if we add to the hazard function a probability current proportional to the derivative of the voltage. Stochastic resonance in response to periodic input occurs in both noise models and exhibits similar characteristics.

A new linearization technique for MOSFET RF amplifier using multiple gated transistors

Abstract: A simple linearization technique using multiple gated common source transistors is proposed where gate width and gate drive (V/sub gs/-V/sub th/) of each transistor are chosen to compensate for the nonlinear characteristics of the main transistor. To demonstrate the feasibility of this approach, a prototype double-gated RF amplifier using two MOSFETs is implemented and its RF characteristics are compared with those of a single one. The results show that, compared with a conventional single-gate transistor amplifier, the third order intermodulation (IMD/sub 3/) is improved by 6 dB with similar gain, fundamental output power, and DC power consumption. Because the auxiliary transistor is smaller than the main one and biased at subthreshold, adding this does not affect amplifier characteristics appreciably other than the nonlinearity. With further optimization using multiple gated transistors, much better nonlinear performance per power consumption would be expected.

Subthreshold voltage noise due to channel fluctuations in active neuronal membranes.

Abstract: Voltage-gated ion channels in neuronal membranes fluctuate randomly between different conformational states due to thermal agitation. Fluctuations between conducting and nonconducting states give rise to noisy membrane currents and subthreshold voltage fluctuations and may contribute to variability in spike timing. Here we study subthreshold voltage fluctuations due to active voltage-gated Na+ and K+ channels as predicted by two commonly used kinetic schemes: the Mainen et al. (1995) (MJHS) kinetic scheme, which has been used to model dendritic channels in cortical neurons, and the classical Hodgkin-Huxley (1952) (HH) kinetic scheme for the squid giant axon. We compute the magnitudes, amplitude distributions, and power spectral densities of the voltage noise in isopotential membrane patches predicted by these kinetic schemes. For both schemes, noise magnitudes increase rapidly with depolarization from rest. Noise is larger for smaller patch areas but is smaller for increased model temperatures. We contrast the results from Monte Carlo simulations of the stochastic nonlinear kinetic schemes with analytical, closed-form expressions derived using passive and quasi-active linear approximations to the kinetic schemes. For all subthreshold voltage ranges, the quasi-active linearized approximation is accurate within 8% and may thus be used in large-scale simulations of realistic neuronal geometries.

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

Abstract: High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique

Abstract: A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 /spl mu/m Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 /spl Aring/ gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage.

A minimum total power methodology for projecting limits on CMOS GSI

Abstract: A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact "transregional" MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.

Analysis of submicron carbon nanotube field-effect transistors

Abstract: A theoretical analysis of carbon nanotube based field-effect transistors fabricated by two different groups [Tans et al, Nature (London) 393, 49 (1998); Martel et al, Appl Phys Lett 73, 2447 (1998)] is presented The metal (electrode)-semiconductor (nanotube) contact influences subthreshold channel conductance versus gate voltage VG, such that the occurrence of a kink depends on the transport mechanism across this contact Saturation in the turn-on drain current ID vs VG seen in experiments reflects the nanotube state density Saturationless ID versus drain voltage VD indicates transport in the weak-localization regime in the absence of carrier–carrier scattering so that pinch-off cannot occur To compensate for saturationless ID(VD) in digital applications, nanotube transistors need to be designed to maximize their transconductance

Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias

Abstract: We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage. key words: MOSFET, low power, low voltage, variable thresh-

A p-channel MOS synapse transistor with self-convergent memory writes

Abstract: We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications. The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight. We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems.

New simple procedure to determine the threshold voltage of MOSFETs

Abstract: A new alternative technique is proposed to extract the threshold voltage from the subthreshold-to-strong inversion transition region of MOSFETs. It uses an auxiliary operator that involves integration of the drain current as a function of gate voltage. Tests show that the procedure produces results comparable to conventional methods.

Transistor characteristics of 14-nm-gate-length EJ-MOSFETs

Abstract: We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFETs) to investigate transport characteristics of ultrafine gate MOSFETs. By using EB direct writing on an ultrahigh-resolution negative resist (calixarene), we could achieved a gate length of only 14 nm. Despite such an ultrafine gate, the device exhibited transistor operation at room temperature. From studying the devices with the gate lengths from 14 nm to 98 nm, we found that when the gate length was below 30 nm the subthreshold leakage current increased. The low-temperature measurements showed that the leakage current was caused by the classical thermal process and that quantum effects do not play an important role in subthreshold characteristics at room temperature.

1/f noise modeling in long channel amorphous silicon thin film transistors

Abstract: 1/f noise investigations in thin film transistors with long channel and thin thickness of amorphous silicon film are presented. It is found that the noise behavior follows the mobility fluctuation model in ohmic and saturation regimes, whereas in the subthreshold conduction, a quadratic law versus the drain current is observed. The noise modeling is proposed taking into account the equations usually utilized for crystalline silicon metal–oxide–semiconductor field-effect transistors according to Hooge’s theory. Moreover, the Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model is adapted to predict the noise levels. Two noise parameters have been extracted: The first is used in the subthreshold region, whereas we show that the second, directly related to Hooge’s parameter, is adequate to describe alone the noise in normal conduction up to the saturation.

Analysis of the activation energy of the subthreshold current in laser- and solid-phase-crystallized polycrystalline silicon thin-film transistors

Abstract: Analysis of the thermal and gate-voltage dependences of the current in the subthreshold region is performed on both low-temperature laser-crystallized and solid-phase-crystallized polycrystalline silicon (polysilicon) thin-film transistors (TFTs). Temperature measurements are made at first in order to extract the variations of the activation energy EA of the drain current with the gate voltage. The plot of the subthreshold current versus the measured activation energy leads to an apparent activation energy EA/n, where the n factor is extracted from the slope of this plot. The n factor is close to 1 for laser-crystallized polysilicon TFTs while it is rather close to 2 for solid-phase-crystallized ones. These two values can be attributed to a different defect distribution in the two differently crystallized TFTs polysilicon active layers.

Subthreshold and near threshold K + meson photoproduction\newline on nuclei

Abstract: The inclusive K+ meson production in photon–induced reactions in the near threshold and subthreshold energy regimes is analyzed with respect to the one–step (γN→K + Y, Y=Λ,Σ) incoherent production processes on the basis of an appropriate new folding model, which takes properly into account the struck target nucleon removal energy and internal momentum distribution (nucleon spectral function), extracted from recent quasielastic electron scattering experiments and from many–body calculations with realistic models of the NN interaction. Simple parametrizations for the total and differential cross sections of the K+ production in photon–nucleon collisions are presented. Comparison of the model calculations of the K+ differential cross sections for the reaction γ+C12 in the threshold region with the existing experimental data is given, that displays the contributions to the K+ production at considered incident energies coming from the use of the single–particle part as well as high momentum and high removal energy part of the nucleon spectral function. Detailed predictions for the K+ total and differential cross sections from γH2, γC12 and γPb208 reactions at subthreshold and near threshold energies are provided. The influence of the uncertainties in the elementary K+ production cross sections on the K+ yield is explored.

Low power and high performance design challenges in future technologies

Abstract: We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

SPICE models for flicker noise in n-MOSFETs from subthreshold to strong inversion

Abstract: The two main sources of low-frequency flicker noise are mobility fluctuations and number fluctuations. Our experiments on NMOS noise measurements were done from subthreshold to saturation region of operation for both long-channel (5 /spl mu/m) and short-channel (as small as 0.6 /spl mu/m) NMOS transistors. The results suggest that for both types that in the saturation region, the flicker noise is due to the surface state effect and the noise equations, NLEV=2 and 3, in SPICE, HSPICE, and PSPICE are most appropriate. For short-channel devices, due to the effects of velocity saturation and the resulting nonlinear transconductance (g/sub m/) variation with gate bias voltage, the input-referred voltage noise increases as the gate-source voltage increases instead of staying constant as it does for long-channel devices. In the subthreshold region, the input-referred voltage noise decreases drastically as the gate-source voltage increases for both long-channel and short-channel NMOS devices. Simulations have been done using PSPICE and HSPICE, with noise level (NLEV)=3 and device model level 3 and BSIM 3.2 and 3.3. The results from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICE level 3 compare favorably with the measured noise phenomena for the short-channel and long-channel NMOS devices, respectively.

CMOS circuit technology for sub-ambient temperature operation

Abstract: Sub-ambient-temperature operation can remove important device scaling and circuit performance bottlenecks in sub-100 nm CMOS technologies. It permits scaling of supply voltages of high-speed circuits to sub-1 V by reducing the subthreshold currents and increasing the carrier mobility in the channels, lowers interconnection resistances significantly, and eliminates electromigration-related failure mechanisms. This paper analyzes the advantages of reduced temperature operation at the circuit level for server applications, while the accompanying paper describes refrigeration techniques for sub-ambient temperature operation.

Simulation and optimization of strained Si1-xGex buried channel p-MOSFETs

Abstract: Deep submicron (0.35 μm) strained Si1−xGex buried channel p-MOSFETs with a Ge concentration up to 50% were simulated using the MEDICI device simulator. A buried channel structure offers several benefits over a surface channel structure without a Si cap. Simulation results show that the maximum drain current increases monotonically with the Ge mole fraction. The drive current enhancement is more than 300% for Si0.5 Ge0.5 over Si. Subthreshold characteristics were analyzed for different Ge mole fractions in this study. The effects of Si cap layer thickness and Si1−xGex channel thickness on drive current and gate voltage operating window were analyzed. The simulation results show that the drive current is the highest when the Si1−xGex layer thickness is between 100 and 300 A and that Si1−xGex layer thickness can be as low as 50 A with less than 10% penalty in the drive current, for structures with a 50 A Si cap layer.

Test challenges in nanometer technologies

Abstract: Scaling transistor feature size allows greater density, higher performance and lower cost. The unrelenting pursuit of device scaling has enabled MOS gate dimensions to be reduced from 10/spl middot/m in the 1970's to a present day size of 0.1/spl middot/m. Conventional scaling of gate oxide thickness, source/drain extension, junction depths, and gate lengths have brought about several new technology issues invalidating some earlier methods for resting ICs. To enable testing devices into the 21/sup st/ century, new approaches are required in both test and design for testability. In this paper, we define the problems that arise with device scaling such as gate oxide leakage, subthreshold leakage, power density, electromigration, and soft error problems in qualitative and quantitative terms. The latter half of the paper deals with some of the solutions being pursued at Intel.

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics

Abstract: We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (0.7 V). By using this technology, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with mid-gap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).

1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

Abstract: Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-V/sub th/ nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words/spl times/16-bits SRAM test chip, fabricated with a 0.35-/spl mu/m MTCMOS/SIMOX process (shortened effective channel length of 0.17 /spl mu/m is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-/spl mu/W and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads.

Photoelectric converting device

Abstract: In a photoelectric converting device, a photoelectric current (electric signal) generated by light entering a photodiode PD causes the gate voltage of MOS transistors T1 and T2 to rise, and thus a current corresponding to this gate voltage flows through the MOS transistor T2 into a capacitor C, shifting the voltage at the node “a” between the MOS transistor T2 and the capacitor C. Here, when the voltage φVPS applied to the source of the MOS transistor T1 is adjusted in such a way that the MOS transistor T1 operates in a subthreshold region below its threshold level, the voltage at the node “a” varies on a natural-logarithm basis with respect to the photoelectric current. By contrast, when the voltage φVPS applied to the source of the MOS transistor T1 is kept approximately equal to a direct-current voltage VPD, the voltage at the node “a” varies on a linear basis with respect to the photoelectric current.

Semiconductor device including interface circuit, logic circuit, and static memory array having transistors of various threshold voltages and being supplied with various supply voltages

Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.