Showing papers on "Subthreshold conduction published in 2001"

Device scaling limits of Si MOSFETs and their application dependencies

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs

Abstract: A one-dimensional (1-D) analytic solution is derived for an undoped (or lightly doped) double-gate (DG) MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution is applied to both symmetric and asymmetric DG MOSFETs to obtain closed forms of band bending and inversion charge as a function of gate voltage and silicon thickness. It is shown that for the symmetric DG device, "volume inversion" only occurs under subthreshold conditions, with a slightly negative impact on performance. Comparisons under the same off-state conditions show that the on-state inversion charge density of an asymmetric DG with one channel is only slightly less than that of a symmetric DG with two channels, if the silicon film is thin. From the analytic solutions, explicit expressions for the various components of the equivalent capacitance circuit are derived for symmetric and asymmetric DG devices. These help gain an insight into the electrostatic coupling between the back gate and the front channel in the asymmetric case. Finally, the gate work function requirements are quantified for symmetric and asymmetric DG CMOS, based on threshold voltage considerations.

Solid-state image-sensing device

Abstract: A solid-state image-sensing device has a photosensitive element that produces an electric signal commensurate with the amount of light incident thereon, a transistor of which the first electrode and the control electrode are connected to one electrode of the photosensitive element, and a resetting portion for resetting the transistor by feeding a predetermined pulse signal to the second electrode of the transistor The resetting portion resets the transistor in such a way as to inhibit the transistor from operating in a subthreshold region when the amount of light incident on the photosensitive element is below a predetermined level

MOSFET Models for SPICE Simulation: Including BSIM3v3 and BSIM4

Abstract: Preface. 1 Modeling Jargons. 1.1 SPICE Simulator and SPICE Model. 1.2 Numerical Iteration and Convergence. 1.3 Digital vs. Analog Models. 1.4 Smoothing Function and Single Equation. 1.5 Chain Rule. 1.6 Quasi-Static Approximation. 1.7 Terminal Charges and Charge Partition. 1.8 Charge Conservation. 1.9 Non-Quasi-Static and Quasi-Static y-Parameters. 1.10 Source-Referencing and Inverse Modeling. 1.11 Physical Model and Table-Lookup Model. 1.12 Scalable Model and Device Binning. References and Notes. 2 Basic Facts About BSIM3. 2.1 What Is and What's Not Implemented in BSIM3. 2.2 DC Equivalent Circuit Model. 2.3 BSIM3's ^-Parameters. 2.4 Large-Signal Equivalent Circuit. 2.5 Small-Signal Model. 2.6 Noise Equivalent Circuit. 2.7 Special Operating Conditions: VDS 0, VGS 0> . References and Notes. 3 BSIM3 Parameters. 3.1 List of Parameters According to Function. 3.2 Alphabetical Glossary of BSIM3 Parameters. 3.3 Flow Diagram of SPICE Simulation. References and Notes. 4 Improvable Areas of BSIM3. 4.1 Lack of Robust Non-Quasi-Static Models: Transient Analysis. 4.2 Problem with the 40/60 Partition: The "Killer NOR Gate". 4.3 Lack of Channel Resistance (NQS Effect Small-Signal Analysis). 4.4 Incorrect Transconductance Dependency on Frequency. 4.5 Lack of Gate Resistance (and Associated Noise). 4.6 Lack of Substrate Distributed Resistance (and Associated Noise). 4.7 Incorrect Source/Drain Asymmetry at VDS = 0. 4.8 Incorrect Cgb Behaviors. 4.9 Capacitances with Wrong Signs. 4.10 Cgg Fit and Other Capacitance Issues. 4.11 Insufficient Noise Modeling (No Excess Short-Channel Thermal Noise). 4.12 Insufficient Noise Modeling (No Channel-Induced Gate Noise). 4.13 Incorrect Noise Figure Behavior. 4.14 Inconsistent Input-Referred Noise Behavior. 4.15 Possible Negative Transconductances. 4.16 Lack of GIDL (Gate-Induced Drain Leakage) Current. 4.17 Incorrect Subthreshold Behaviors. 4.18 Threshold Voltage Rollup. 4.19 Problems Associated with a Nonzero RDSW. 4.20 Other Nuisances. References and Notes. 5. Improvements in BSIM4. 5.1 Introduction. 5.2 Physical and Electrical Oxide Thicknesses. 5.3 Strong Inversion Potential for Vertical Nonuniform Doping Profile. 5.4 Threshold Voltage Modifications. 5.5 VGST^ in Moderate Inversion. 5.6 Drain Conductance Model. 5.7 Mobility Model. 5.8 Diode Capacitance. 5.9 Diode Breakdown. 5.10 GIDL (Gate-Induced Drain Leakage) Current. 5.11 Bias-Dependent Drain-Source Resistance. 5.12 Gate Resistance. 5.13 Substrate Resistance. 5.14 Overlap Capacitance. 5.15 Thermal Noise Models. 5.16 Flicker Noise Model. 5.17 Non-Quasi-Static AC Model. 5.18 Gate Tunneling Currents. 5.19 Layout-Dependent Parasitics. References and Notes. Appendixes. A BSIM3 Equations. B Capacitances and Charges for All Bias Conditions. C Non-Quasi-Static ^-Parameters. D Fringing Capacitance. E BSIM3 Non-Quasi-Static Modeling. F Noise Figure. G BSIM4 Equations. Index.

Robust subthreshold logic for ultra-low power operation

Abstract: Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

Robust subthreshold logic for ultra-low power operation

Abstract: Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

A 50 nm depleted-substrate CMOS transistor (DST)

Abstract: In this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates significant performance gain over bulk Si transistors without the floating body effect (FBE). We have fabricated depleted-substrate CMOS transistors on thin silicon body (/spl les/30 nm) with physical gate lengths down to 50 nm which show much steeper subthreshold slopes (/spl les/75 mV/decade) and improved DIBL (/spl les/50 mV/V) over both partially-depleted (P-D) SOI and bulk Si, for both PMOS and NMOS transistors. The salicide formation and high parasitic resistance problems associated with the use of thin Si body can be overcome by using raised source/drain. Depleted-substrate PMOS transistors with 50 nm physical gate length and raised source/drain were fabricated and achieved I/sub on/=0.65 mA/um and I/sub off/=9 nA/um at V/sub cc/=1.3 V. This PMOS drive current is the highest ever reported, and is about 30% higher than any previously published PMOS I/sub on/ value for both PD-SOI and bulk Si at a given I/sub off/. The use of raised source/drain improved the I/sub on/ of the depleted-substrate NMOS transistors by /spl sim/20%. Depleted-substrate NMOS transistors with 65 nm physical gate length and raised source/drain achieved DIBL=45 mV/V, subthreshold slope=75 mV/decade, I/sub on/=1.18 mA/um and I/sub off/ =60 nA/um at V/sub cc/=1.3 V, as well as significant improvement in Id-Vd characteristics due to a 60% reduction in DIBL and >25% improvement in subthreshold slope over the bulk Si.

1/f noise in CMOS transistors for analog applications

Abstract: Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two "low noise" CMOS processes of 2 /spl mu/m and 0.5 /spl mu/m technologies are compared and it is found that the more advanced process, with 0.5 /spl mu/m technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.

Synaptic noise improves detection of subthreshold signals in hippocampal CA1 neurons.

Abstract: Stochastic resonance (SR) is a phenomenon whereby the detection of a low-level signal is enhanced in a nonlinear system by the introduction of noise. Studies of the effects of SR in neurons have suggested that noise could play a prominent role in improving detection of small signals. Most experimental SR research has focused on the role of noise in sensory neurons using physiological stimuli. Computer simulations show that signal detection in hippocampal neurons is improved by the addition of physiological levels of noise applied extracellularly to synaptic inputs. These results were confirmed experimentally. We now report that endogenous noise sources can also improve signal detection. The noise source was generated by modulating the random synaptic activity on the apical dendrites of CA1 cells in rat hippocampal slices using subthreshold cathodic current. Intracellular recordings of CA1 cells showed that even small increases of synaptic noise are able to greatly improve the detection of an independent, synaptic, subthreshold stimulus as predicted by the simulations. The noise variance in the CA1 cell was compared with the resting variance and with variance changes caused by several endogenous noise sources. In all cases, the increased noise variance was well within the physiological range. These results were supplemented and analyzed with a CA1 computer model. The improved signal detection with small amounts of endogenous noise suggests that the diverse inputs to CA1 are able to improve detection of subthreshold synaptic signals and could provide a means to modulate detection of specific inputs in the hippocampus.

Subtractive and Divisive Inhibition: Effect of Voltage-Dependent Inhibitory Conductances and Noise

Abstract: The influence of voltage-dependent inhibitory conductances on firing rate versus input current (f-I) curves is studied using simulations from a new compartmental model of a pyramidal cell of the weakly electric fish Apteronotus leptorhynchus. The voltage dependence of shunting-type inhibition enhances the subtractive effect of inhibition on f-I curves previously demonstrated in Holt and Koch (1997) for the voltage-independent case. This increased effectiveness is explained using the behavior of the average subthreshold voltage with input current and, in particular, the nonlinearity of Ohm's law in the subthreshold regime. Our simulations also reveal, for both voltage-dependent and -independent inhibitory conductances, a divisive inhibition regime at low frequencies (f 40 Hz). A simple leaky integrate-and-fire type model that incorporates the voltage dependence supports the results from our full ionic simulations.

Low-power CMOS at Vdd = 4kT/q

Abstract: Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic.

Voltage-Gated Sodium Channels Shape Subthreshold EPSPs in Layer 5 Pyramidal Neurons From Rat Prefrontal Cortex

Abstract: The role of voltage-dependent channels in shaping subthreshold excitatory postsynaptic potentials (EPSPs) in neocortical layer 5 pyramidal neurons from rat medial prefrontal cortex (PFC) was invest...

Comparison of MOSFET-threshold-voltage extraction methods

Abstract: The difference in MOSFET threshold voltages caused by the difference in the extraction method is studied, by measuring and analyzing its dependencies on channel length, substrate voltage and drain voltage. It is found that the standard deviation of the difference between threshold voltages caused by the difference in the extraction method is less than that of the threshold voltage itself in a wafer. The dependencies of the threshold voltage on channel length, extracted from the drain current data around the threshold voltage, however, show different behavior from those extracted from the drain current data only in the subthreshold region or only in the ON region. It is considered that “channel-length modulation” causes this different behavior and, therefore, that those extraction methods are not desirable.

Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits

Abstract: A compensation circuit for transistor threshold voltages in integrated circuits is described. The compensation circuit includes a transistor, current source, and gate reference voltage supply. The transistor is biased to provide a well bias voltage, or backgate voltage VBG, which is coupled to transistors provided on a common integrated circuit. This compensation circuit eliminates the need for gate biasing capacitors, and provides flexibility in setting threshold voltages in low voltage circuits. The gate reference voltage and current source are established to provide a desired backgate voltage VBG. Compensation circuits are described for both n-channel and p-channel transistors. A memory device is described which includes compensation circuits for controlling threshold voltages of transistors provided therein.

A new empirical large-signal model of Si LDMOSFETs for high-power amplifier design

Abstract: We propose a new empirical large-signal model of silicon laterally diffused MOSFETs for the design of various modes of high-power amplifiers. The new channel current model has only nine parameters that represent the unique operation principles of a MOSFET. In the channel current model, we include the thermal phenomena of high-power devices. To accurately characterize high-power devices, we incorporate the channel heating and heat-sink heating effects by providing two thermal capacitances and two thermal resistances. Nonlinear capacitances, including deep subthreshold and triode regions, as well as normal saturation regions, are extracted and modeled. For validation of our model, a 1.4-GHz 5-W amplifier is implemented, and the measured and simulated results match very well.

Subthreshold stimulator for angiogenesis

Abstract: The present invention provides a novel stimulatory device for the controlled production of angiogenic growth factors. More specifically, the present invention provides a subthreshold pulse generator for the local production of vascular endothelial growth factor.

Dual threshold gate array or standard cell power saving library circuits

Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.

Body bias dependence of 1/f noise in NMOS transistors from deep-subthreshold to strong inversion

Abstract: Dependence of 1/f noise on the body-to-source junction bias voltages (V/sub BS/) between -25 and 05 V for 025-/spl mu/m NMOS transistors is reported In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 05 V (V/sub BS/) compared to that for V/sub BS/=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias On the contrary, in strong inversion, 1/f noise remains almost constant for the entire V/sub BS/ range

Unified MOSFET compact I-V model formulation through physics-based effective transformation

Abstract: A one-region compact I/sub ds/ model from subthreshold to saturation, which resembles the same form as the well-known long-channel model but includes all major short-channel effects (SCEs) in deep-submicron (DSM) MOSFETs, has been formulated through physics-based effective transformation. The model has 23 process-dependent fitting parameters, which requires an 11-step, one-iteration extraction procedure. The new approach to modeling channel-length modulation (CLM), subthreshold diffusion current, and edge-leakage current, all in a compact form, has been verified with the 0.25-/spl mu/m experimental data. The model covers the full range of gate length (without "binning") and bias conditions, and can be correlated to true process variables for aiding technology development.

Infrared micropulsed laser treatment for diabetic macular edema--subthreshold versus threshold lesions.

Abstract: Purpose. To assess the effectiveness of subthreshold (invisible after placement) and threshold (barely visible after placement) 810 nm laser photocoagulation in the treatment of clinically significant diabetic macular edema. Methods. A grid of subthreshold laser spots was used to treat patients with diabetic edema. Retrospectively, the results of treatment of 20 eyes of 20 patients were compared to the results of treatment of 120 eyes of 120 patients using a grid of threshold laser lesions. Results. At six months, 60% of subthreshold treated eyes and 75% of threshold treated eyes showed anatomic resolution of macular edema. Improvement or stabilization of visual acuity was achieved in 85% of threshold or subthreshold treated eyes. Conclusion. Gentle grid treatment of regions of diabetic macular edema was effective in ameliorating the edema and limiting visual loss. Subthreshold laser was less effective in promoting resolution of edema compared to threshold lesions, though the difference was not significan...

Physics and applications of the Schottky junction transistor

Abstract: This paper presents the results from numerical simulations of a novel subthreshold transistor configuration. The device uses the input current from a forward-biased Schottky gate to control the larger current flowing in a depleted channel. Analytical approximations are used to derive the current gain of the transistor. The numerical simulations confirm the analytical derivation and show that a 0.5 /spl mu/m gate length device would have a cutoff frequency approaching 10 GHz for supply voltages less than 0.5 V. Possible applications of the device in the areas of micropower analog circuits and ULSI logic are discussed.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce decrease of a threshold voltage caused by short channel effect, deterioration of subthreshold characteristic, decrease of punch through withstanding voltage, etc., and can realize microstructure by having different threshold voltages in the same chip and constituting the entire device by using surface channel transistors, and a manufacturing method of a semiconductor device wherein manufacturing is enabled without needing an additional process and a mask. SOLUTION: In this semiconductor device, an N well diffusion layer 2 and a P well diffusion layer 3 which are arranged adjacently are disposed. A P gate PMOS transistor 100 having a P-type gate electrode 71 and an N gate PMOS transistor 101 having an N-type gate electrode 72 are formed in the same N well diffusion layer 2. A P gate NMOS transistor 200 having a P-type gate electrode 71 and an N gate NMOS transistor 201 having an N-type gate electrode 72 are formed in the same P well diffusion layer 3.

Inversion charge modeling

Abstract: A simple, implicit, relation for the inversion charge density in the channel of metal oxide semiconductor (MOS) transistors is presented. The relation is continuous and covers the whole operating range, from subthreshold to strong inversion. The derivative of the local inversion charge density with respect to the channel voltage is a simple expression in the charge density, leading to analytic integrals as required for obtaining the drain current and the capacitance coefficients.

Statistical analysis of stochastic resonance with ergodic diffusion noise

Abstract: A subthreshold signal is transmitted through a channel and may be detected when some noise -- with known structure and proportional to some level -- is added to the data. There is an optimal noise level, called stochastic resonance, that corresponds to the highest Fisher information in the problem of estimation of the signal. As noise we consider an ergodic diffusion process and the asymptotic is considered as time goes to infinity. We propose consistent estimators of the subthreshold signal and we solve further a problem of hypotheses testing. We also discuss evidence of stochastic resonance for both estimation and hypotheses testing problems via examples.

Threshold voltage definition and extraction for deep-submicron MOSFETs

Abstract: The subtle difference in MOSFET threshold voltage between the two popular definitions, maximum- g m and constant current, is investigated in the deep-submicron regime. The result pinpoints to the importance of the lateral-field effect in linear region at very short gate length, and further supports the combined definition known as the “critical current at linear threshold” method, which includes short-channel effects while retaining the simplicity and consistency of the constant-current method.

Implementation of hot-carrier reliability simulation in Eldo

Abstract: The implementation of all components of hot-carrier reliability simulation in Eldo is described in this paper. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. Two approaches for modeling the degraded MOS transistor have been implemented, namely, the parameter fitting method and a newly proposed /spl Delta/I/sub d/ model. The new model overcomes the discontinuity and subthreshold invalidity of the existing models. The model has proven high accuracy for two well known foundries on their 0.25 /spl mu/m technologies. Simulation is results on some direct applications like inverters and ring oscillator circuits are also presented in this paper.

A sub 40-nm body thickness n-type FinFET

Abstract: We experimentally demonstrate near-ideal subthreshold behavior of fully-depleted fin-style double-gate n-type MOSFETs and the best measured transconductance Gm-sat = 72 S/m (>400 S/m intrinsic) for sub-40 nm n-type FinFETs reported. This silicon nFET exhibits experimental ideality n = 1.13, in good agreement with the deviation from unity expected due only to source/drain coupling. These results comprise the best behavior for 100 nm-scale double-gate nFETs in terms of channel subthreshold characteristics and gate leakage observed experimentally to date. Hisamoto et al. (1989) introduced experimental results on doubld-gate silicon MOSFETs in which the channel is formed by etching single-crystal silicon to leave a vertical fin standing, forming a gate which wraps around the fin, with source and drain regions on the two ends of the fin. This basic idea was further refined to sub-50 nm n-type MOSFETs and then extended to sub-50 nm p-type MOSFETs. Using simplified fabrication techniques, we demonstrate improved behavior, from an intrinsic channel point of view, of the nFET work, using conventional CMOS integration on n-type FinFETs.

Subthreshold leakage control techniques for low power digital circuits

Abstract: Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. As a result, new techniques are needed in order to provide high performance and low power circuit operation. This dissertation develops new circuit techniques that exploit dual threshold voltages and body biasing in order to reduce subthreshold leakage currents in both standby and active modes. To address standby leakage currents, a novel sleep transistor sizing methodology for MTCMOS circuits was developed and new “imbedded” dual Vt techniques were described that could provide better performance and less area overhead by exploiting different logic styles. Work was also done to develop new MTCMOS sequential circuits, which include a completely novel way to hold state during standby modes. Body biasing circuit techniques were also explored to provide dynamic tuning of device threshold voltages to tune out parameter and temperature variations during the active state. This not only helps reduce active leakage currents but also improves process yields as well. A final research direction explored optimal VCC/Vt tuning during the active modes as a function of varying workloads and temperatures so that a chip can automatically be configured to operate at the lowest energy level that balances subthreshold leakage power and dynamic switching power. Through novel circuit techniques and methodologies, this work illustrates how subthreshold leakage currents can be controlled from a circuit perspective, thereby helping to enable continued aggressive scaling of semiconductor technologies. Thesis Supervisor: Anantha P. Chandrakasan Title: Associate Professor of Electrical Engineering

Novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI for the improvement of data retention time in gigabit density DRAM and beyond

Abstract: In this paper, we propose a novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-/spl mu/m technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si/sub 3/N/sub 4/-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-/spl mu/m technology and beyond.

High speed DRAM local bit line sense amplifier

Abstract: Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C 1, generating a voltage swing delta V 1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb 1 with small voltage swing delta Vb 1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.