Showing papers on "Subthreshold conduction published in 2002"

Carbon nanotube electronics

Abstract: Presents experimental results on single-wall carbon nanotube field-effect transistors (CNFETs) operating at gate and drain voltages below 1V. Taking into account the extremely small diameter of the semiconducting tubes used as active components, electrical characteristics are comparable with state-of-the-art metal oxide semiconductor field-effect transistors (MOSFETs). While output as well as subthreshold characteristics resemble those of conventional MOSFETs, we find that CNFET operation is actually controlled by Schottky barriers (SBs) in the source and drain region instead of by the nanotube itself. Due to the small size of the contact region between the electrode and the nanotube, these barriers can be extremely thin, enabling good performance of SB-CNFETs.

I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q

Abstract: One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

FinFET design considerations based on 3-D simulation and analytical modeling

Abstract: Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.

Analog VLSI: Circuits and Principles

Abstract: From the Publisher: Neuromorphic engineers work to improve the performance of artificial systems through the development of chips and systems that process information collectively using primarily analog circuits. This book presents the central concepts required for the creative and successful design of analog VLSI circuits. The discussion is weighted toward novel circuits that emulate natural signal processing. Unlike most circuits in commercial or industrial applications, these circuits operate mainly in the subthreshold or weak inversion region. Moreover, their functionality is not limited to linear operations, but also encompasses many interesting nonlinear operations similar to those occurring in natural systems. Topics include device physics, linear and nonlinear circuit forms, translinear circuits, photodetectors, floating-gate devices, noise analysis, and process technology.

Subthreshold leakage modeling and reduction techniques

Abstract: As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual Vt partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.

A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Abstract: In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an optimal V/sub DD//V/sub t/ operating point that minimizes total active power consumption for different workload and operating conditions. A 175-mV multiply-accumulate test chip using a triple-well technology with tunable supply and body bias values is measured to experimentally verify the tradeoffs between the various sources of power. The test chip shows that there is an optimum V/sub DD//V/sub t/ operating point, although it differs from the theoretical limit because of excessive forward bias currents. Finally, we propose a preliminary automatic supply and body biasing architecture (ASB) that automatically configures a circuit to operate with the lowest possible active power consumption.

Nanotechnology goals and challenges for electronic applications

Abstract: Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-/spl mu/m generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.

Subthreshold characteristics of field effect transistors based on poly(3-dodecylthiophene) and an organic insulator

Abstract: The properties of field effect transistors with organic insulator and semiconducting regions, fabricated with a top-gate architecture, have been investigated. Thin films (d≈30 nm) of regioregular poly(3-dodecylthiophene) were employed as the active semiconductor and the gate insulator was formed by a 500-nm-thick layer of poly(4-vinylphenol). Both were solution-processed on top of poly(ethylenetherephthalate) films, which were used as substrates. The output characteristics show a pronounced saturation behavior with an unconventional nonquadratic saturation current dependence on the gate voltage. Hence the (hole) mobility of 0.002–0.005 cm2/Vs has been estimated from the linear region of the transfer characteristics. The transistor turn-on occurs at a threshold voltage of approximately Vth=0 V, and the device can be operated with a supply voltage of between 15 and 20 V. As is usually observed for organic transistors, the inverse subthreshold slope (S) is very high, in our case S≈7 V/dec, by contrast with S...

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Abstract: Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

Frequency selectivity of layer II stellate cells in the medial entorhinal cortex.

Abstract: Electrophysiologically, stellate cells (SCs) from layer II of the medial entorhinal cortex (MEC) are distinguished by intrinsic 4- to 12-Hz subthreshold oscillations. These oscillations are thought to impose a pattern of slow periodic firing that may contribute to the parahippocampal theta rhythm in vivo. Using stimuli with systematically differing frequency content, we examined supra- and subthreshold responses in SCs with the goal of understanding how their distinctive characteristics shape these responses. In reaction to repeated presentations of identical, pseudo-random stimuli, the reliability (repeatability) of the spiking response in SCs depends critically on the frequency content of the stimulus. Reliability is optimal for stimuli with a greater proportion of power in the 4- to 12-Hz range. The simplest mechanistic explanation of these results is that rhythmogenic subthreshold membrane mechanisms resonate with inputs containing significant power in the 4- to 12-Hz band, leading to larger subthreshold excursions and thus enhanced reliability. However, close examination of responses rules out this explanation: SCs do show clear subthreshold resonance (i.e., selective amplification of inputs with particular frequency content) in response to sinusoidal stimuli, while simultaneously showing a lack of subthreshold resonance in response to the pseudo-random stimuli used in reliability experiments. Our results support a model with distinctive input-output relationships under subthreshold and suprathreshold conditions. For suprathreshold stimuli, SC spiking seems to best reflect the amount of input power in the theta (4-12 Hz) frequency band. For subthreshold stimuli, we hypothesize that the magnitude of subthreshold theta-range oscillations in SCs reflects the total power, across all frequencies, of the input.

Potassium currents during the action potential of hippocampal CA3 neurons.

Abstract: Central neurons have multiple types of voltage-dependent potassium channels, whose activation during action potentials shapes spike width and whose activation and inactivation at subthreshold voltages modulate firing frequency. We characterized the voltage-dependent potassium currents flowing during the action potentials of hippocampal CA3 pyramidal neurons and examined the susceptibility of the underlying channel types to inactivation at subthreshold voltages. Using acutely dissociated neurons that permitted rapid voltage clamp, action potentials recorded previously were used as the command voltage waveform, and individual components of potassium current were identified by pharmacological sensitivity. The overall voltage-dependent potassium current in the neurons could be split into three major components based on pharmacology and kinetics during step voltage pulses: I(D) (fast activating, slowly inactivating, and sensitive to 4-aminopyridine at 30 microm), I(A) (fast activating, fast inactivating, and sensitive to 4-aminopyridine at 3 mm), and I(K) (slowly activating, noninactivating, and sensitive to external TEA at 3-25 mm). The potassium current during the action potential was composed of approximately equal contributions of I(D) and I(A), with a negligible contribution of I(K). I(D) and I(A) had nearly identical trajectories of activation and deactivation during the action potential. Both I(A) and I(D) showed steady-state inactivation at subthreshold voltages, but maximal inactivation at such voltages was incomplete for both currents. Because of the major contribution of both I(D) and I(A) to spike repolarization, it is likely that modulation or partial inactivation at subthreshold voltages of either current can influence spike timing with minimal effect on spike width.

Hole transport in polycrystalline pentacene transistors

Abstract: Measurements of pentacene thin-film transistors are used to explore hole transport mechanisms. The grain-boundary barrier model does not account for the data, since no field dependence of the mobility is observed over a wide range of gate and drain voltages. Instead, trapping provides a more satisfactory qualitative and quantitative interpretation. The subthreshold characteristics are attributed to deep acceptors in the pentacene film, and the conclusions are supported by numerical modeling.

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range

Abstract: A CMOS variable-gain amplifier (VGA) using subthreshold exponential region transistors with master-slave control technique is proposed. The proposed technique is applied to an intermediate-frequency VGA with a quadrature demodulator for wireless receivers. The test chip is fabricated using a 0.25-/spl mu/m CMOS technology. An 80-dB linearly controlled gain range is achieved with exponential voltage-to-current converters using MOS transistors biased in a subthreshold exponential region, and the master-slave control circuits make the gain-control characteristic insensitive to the temperature. The experimental results indicate that the proposed technique is effective for a CMOS variable-gain amplifier.

Dynamic V/sub t/ SRAM: a leakage tolerant cache memory for low voltage microprocessors

Abstract: This paper presents a Dynamic V/sub t/ SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The V/sub t/ of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high V/sub t/ only when it is not likely to be accessed anymore. Simulation results from the SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processors

Abstract: In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (V/sub TH/-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V/sub TH/-hopping is shown to reduce the power to 18 % of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V/sub TH/-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V/sub TH/-hopping, a small-scale RISC processor with V/sub TH/-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-/spl mu/m CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86% power saving can be achieved by using V/sub TH/-hopping compared with the fixed positive back-gate bias scheme.

Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells

Abstract: The aim of this paper is to achieve a correct description of the programming charge distribution in NROM memory devices. This is essential to prove device functionality and to extrapolate scaling limits of devices. For this purpose we employ an inverse modeling based methodology using measurements easily performed, such as subthreshold characteristics and threshold voltage measurements. We show a simple model of programming charge distribution that can be easily implemented in two-dimensional (2-D) TCAD simulations. Results show good agreement between measured and simulated currents under different bias conditions and for different programming levels.

Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS

Abstract: The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict sub-threshold leakage power of such systems. In this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18 /spl mu/m CMOS confirms the mean error of the model to be 4%. Comparisons of this model to two other existing models that do not take within-die threshold voltage variation into account are also presented.

Enhanced channel mobility of 4H–SiC metal–oxide–semiconductor transistors fabricated with standard polycrystalline silicon technology and gate-oxide nitridation

Abstract: This work presents improved channel mobility of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on 4H–SiC, achieved by gate-oxide nitridation in nitric oxide. Lateral enhancement mode MOSFETs were fabricated using standard polycrystalline silicon gate process and 900 °C annealing for the source and drain contacts. The low field mobility of these MOSFETs was as high as 48 cm2/Vs together with a threshold voltage of 0.6 V, while the interface state density—determined from the subthreshold slope—was about 3×1011 eV−1 cm−2. The 43-nm-thick gate oxide of coprocessed metal–oxide–semiconductor structures exhibited a breakdown field strength of 9 MV/cm.

Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors

Abstract: In this article we investigate the subthreshold behavior of PtSi source/drain Schottky barrier metal–oxide–semiconductor field-effect transistors. We demonstrate very large on/off ratios on bulk silicon devices and show that slight process variations can result in anomalous leakage paths that degrade the subthreshold swing and complicate investigations of device scaling.

Generation and Propagation of Subthreshold Waves in a Network of Inferior Olivary Neurons

Abstract: The cells of the inferior olivary (IO) nucleus generate a large repertoire of electrical signals, among them subthreshold oscillations of the membrane potential (STO). To date, subthreshold oscilla...

Subthreshold leakage modeling and reduction techniques [IC CAD tools]

Abstract: As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual V/sub t/ partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Abstract: Device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and subthreshold slope are quantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (V/sub g2/) and gate work function (/spl Phi//sub m/) control is found to provide superior SCE, V/sub th/ fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

N-channel 3C-SiC MOSFETs on silicon substrate

Abstract: Inversion-mode, n-channel 3C-SiC MOSFETs have been fabricated in a 3C-SiC epilayer grown on a 2°-off-axis Si(001) substrate with optimized SiC processing techniques. Phosphorus implantations are employed for source/drain formation and a sheet resistance of 70 Ω per square is obtained after annealing at 1250°C for 30 min in argon. Both drain characteristics and subthreshold characteristics show typical transistor behavior with an effective channel mobility of 165 cm2/Vs. The breakdown field of the gate oxide is about 3.5 MV/cm.

Analytical subthreshold surface potential model for pocket n-MOSFETs

Abstract: A correct and improved analytical subthreshold surface potential model for pocket n-MOSFETs is proposed. The model is based on solutions of the quasi-two-dimensional (quasi-2-D) Poisson's equation, which satisfy rigorously the boundary conditions of continuity of potential and electric field in the lateral direction along the surface of pocket devices. The closed-form model equations without any fitting empirical formulas efficiently and correctly generate surface potential profiles between the source and drain of deep-submicrometer as well as long-channel pocket n-MOSFETs. Drain-induced barrier lowering (DIBL) effect of deep-submicrometer pocket n-MOSFETs is also predicted by the potential model. The subthreshold surface potential model is applied to off-state current and threshold voltage of deep-submicrometer or sub-100-nm pocket n-MOSFETs.

Subthreshold mental disorders: Nosological and research recommendations.

Abstract: In this chapter, the authors discuss the complicating factors and issues that surround the identification of subthreshold mental conditions. They use depression as the paradigm for other conditions that have subthreshold features.

Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors

Abstract: A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases exponentially as temperature increases. The temperature-adaptive refresh controller selects the refresh period of the memory cells in response to the subthreshold current of a reference transistor. The subthreshold current of the reference transistor increases exponentially as temperature increases As a result, the refresh period is empirically tied to the data retention time. Consequently, the power required for refresh operations decreases as temperature decreases. Power is therefore conserved in applications that operate predominantly at room temperature.

Models for subthreshold and above-threshold currents in 0.1-/spl mu/m pocket n-MOSFETs for low-voltage applications

Abstract: We present a model for subthreshold current in deep-submicrometer pocket n-MOSFETs based on the diffusion current transport equation, the quasi-two-dimensional (2-D) Poisson equation and a doping-density-dependent mobility model, and a model for above-threshold current in deep-submicrometer pocket n-MOSFETs based on the drift-diffusion current transport equation for nonuniformly doped MOSFETs, the charge-sheet approximation, a solution of the one-dimensional (1-D) Poisson equation, a quasi-2-D model for the velocity saturation region, longitudinal- and transverse-field-dependent mobility models. The analytic models for subthreshold and above-threshold currents are used to efficiently construct viable design spaces locating well-designed 0.1-/spl mu/m pocket n-MOSFETs that meet all the device design specifications of off-state (leakage) current, on-state (drive) current, and power-supply voltage. The model for subthreshold current correctly predicts an increase in off-state current in sub-100 nm pocket n-MOSFETs. The model for above-threshold current generates I/sub D/-V/sub DS/ characteristics of a variety of deep-submicrometer pocket n-MOSFETs.

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

Abstract: This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs.