Showing papers on "Subthreshold conduction published in 2004"

Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics

Abstract: High-performance enhancement-mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high-dielectric-constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents and subthreshold swings of 70-80 mV/decade and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scaling. This presents an important advantage over devices with a metal source/drain, or devices commonly referred to as Schottky barrier FETs.

Threshold voltage shift in organic field effect transistors by dipole monolayers on the gate insulator

Abstract: We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional groups. Prior to depositing the organic semiconductors, the organosilanes were applied to the SiO2 gate insulator from solution and form a self-assembled monolayer (SAM). The observed shifts of the transfer characteristics range from −2to50V and can be related to the surface potential of the layer next to the transistor channel. Concomitantly the mobile charge carrier concentration at zero gate bias reaches up to 4×1012∕cm2. In the single crystal FETs the measured transfer characteristics are also shifted, while essentially maintaining the high quality of the subthreshold swing. The shift of the transfer characteristics is governed by the built-in electric field of the SAM and can be explained using a simple energy level diagram. In the thin film devices, the subthreshold re...

Threshold Voltage Shift in Organic Field Effect Transistors by Dipole-Monolayers on the Gate Insulator

Abstract: We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional groups. Prior to depositing the organic semiconductors, the organosilanes were applied to the SiO2 gate insulator from solution and form a self assembled monolayer (SAM). The observed shift of the transfer characteristics range from -2 to 50 V and can be related to the surface potential of the layer next to the transistor channel. Concomitantly the mobile charge carrier concentration at zero gate bias reaches up to 4*10^12/cm^2. In the single crystal FETs the measured transfer characteristics are also shifted, while essentially maintaining the high quality of the subthreshold swing. The shift of the transfer characteristics is governed by the built-in electric field of the SAM and can be explained using a simple energy level diagram. In the thin film devices, the subthreshold region is broadened, indicating that the SAM creates additional trap states, whose density is estimated to be of order 1*10^12/cm^2.

Theoretical and practical limits of dynamic voltage scaling

Abstract: Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs that operate over a much larger voltage range: from full Vdd to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that for subthreshold supply voltages leakage energy becomes dominant, making "just in time completion" energy inefficient. We derive an analytical model for the minimum energy optimal voltage and study its trends with technology scaling. Second, we use the proposed model to study the workload activity of an actual processor and analyze the energy efficiency as a function of the lower limit of voltage scaling. Based on this study, we show that extending the voltage range below 1/2 Vdd will improve the energy efficiency for most processor designs, while extending this range to subthreshold operation is beneficial only for very specific applications. Finally, we show that operation deep in the subthreshold voltage range is never energy-efficient.

Modified derivative superposition method for linearizing FET low noise amplifiers

Abstract: Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

A continuous, analytic drain-current model for DG MOSFETs

Abstract: This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation. The entire I/sub ds/(V/sub g/,V/sub ds/) characteristics for all regions of MOSFET operation: linear, saturation, and subthreshold, are covered under one continuous function, making it ideally suited for compact modeling. By preserving the proper physics, this model readily depicts "volume inversion" in symmetric DG MOSFETs-a distinctively noncharge-sheet phenomenon that cannot be reproduced by standard charge-sheet based I-V models. It is shown that the I-V curves generated by the analytic model are in complete agreement with two-dimensional numerical simulation results for all ranges of gate and drain voltages.

A very low power CMOS mixed-signal IC for implantable pacemaker applications

Abstract: Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

5nm-gate nanowire FinFET

Abstract: A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

A 180mV FFT processor using subthreshold circuit techniques

Abstract: Minimizing energy requires scaling supply voltages below device thresholds. Logic and memory design techniques allowing subthreshold operation are developed and demonstrated. The fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.

Vertical tunnel field-effect transistor

Abstract: The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.

Continuous analytic I-V model for surrounding-gate MOSFETs

Abstract: We present a continuous analytic current-voltage (I-V) model for cylindrical undoped (lightly doped) surrounding gate (SGT) MOSFETs. It is based on the exact solution of the Poisson's equation, and the current continuity equation without the charge-sheet approximation, allowing the inversion charge distribution in the silicon film to be adequately described. It is valid for all the operation regions (linear, saturation, subthreshold) and traces the transition between them without fitting parameters, being ideal for the kernel of SGT MOSFETs compact models. We have demonstrated that the I-V characteristics obtained by this model agree with three-dimensional numerical simulations for all ranges of gate and drain voltages.

A 2-D analytical solution for SCEs in DG MOSFETs

Abstract: A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.

The prevalence and co-morbidity of subthreshold psychiatric conditions

Abstract: Background In previous studies of subthreshold conditions, co-morbidity has been largely ignored. The purpose was to examine rates of co-morbidity among subthreshold disorders and between subthreshold and full-syndrome disorders for the major non-psychotic classes of disorders from DSM-IV. Method Participants came from the Oregon Adolescent Depression Project (mean age=16.6 years; females=52.1%). On the basis of a diagnostic interview (K-SADS), participants were assigned to eight subthreshold disorders (MDD, bipolar, eating, anxiety, alcohol use, substance use, conduct, ADHD). Results Of the 1704 adolescents in the analyses, 52.5% had at least one subthreshood disorder. Of those, 40.0% had also experienced a co-morbid subthreshold condition, and 29.9% of those had a second co-morbid subthreshold condition. Of those with a subthreshold, 36.4% also had a full syndrome. The subthreshold forms of externalizing disorders were co-morbid with each other. As expected, subthreshold anxiety was co-morbid with subthreshold MDD but subthreshold anxiety was also co-morbid with subthreshold alcohol, conduct, and ADHD. The pattern of co-morbidities was nearly identical for males and females. Conclusions The hypotheses that externalizing disorders would be co-morbid with other externalizing disorders and that internalizing disorders would be co-morbid with other internalizing disorders was partially supported. Co-morbidities between subthreshold disorders and between subthreshold disorders and full syndrome should impact future research and clinical practice. The assessment of subthreshold disorders needs to include the assessment of other subthreshold and full-syndrome conditions.

Characterizing and modeling minimum energy operation for subthreshold circuits

Abstract: Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. Solving equations for total energy provides an analytical solution for the Optimum VDD and V/sub T/ to minimize energy for a given frequency in subthreshold operation. SPICE simulations of a 200K transistor FIR filter confirm the analytical solution and the dependence of the minimum energy operating point on important parameters.

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

Abstract: The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.

Gate oxide leakage current analysis and reduction for VLSI circuits

Abstract: In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.

Double gate-MOSFET subthreshold circuit for ultralow power applications

Abstract: In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style

Abstract: A leakage-tolerant design technique for high fan-in dynamic logic circuits is presented. An NMOS transistor with gate and drain terminals tied together (diode) is added in series with the evaluation network of standard domino circuits. Due to the stacking effect, the leakage of the evaluation path significantly decreases, thereby improving the robustness of the circuit against deep-submicron subthreshold leakage and input noise. To improve the speed of the circuit, a current mirror is also employed in the evaluation network to increase the evaluation current. The proposed technique (diode-footed domino) exhibits considerable improvement in leakage and noise immunity as compared to the standard domino circuits. Simulation results of wide fan-in gates designed using Berkeley Predictive Technology Models of 70-nm technology demonstrate at least 1.9/spl times/ noise-immunity improvement at the same delay compared to the standard domino circuits. Dynamic comparators and multiplexers are designed using the diode-footed domino and conventional techniques to demonstrate the effectiveness of the proposed scheme in improving leakage-tolerance and performance of high fan-in circuits.

Film thickness constraints for manufacturable strained silicon CMOS

Abstract: This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

Subthreshold resonance explains the frequency-dependent integration of periodic as well as random stimuli in the entorhinal cortex.

Abstract: Neurons integrate subthreshold inputs in a frequency-dependent manner. For sinusoidal stimuli, response amplitudes thus vary with stimulus frequency. Neurons in entorhinal cortex show two types of ...

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

Abstract: The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.

A 10-nW 12-bit accurate analog storage cell with 10-aA leakage

Abstract: Medium-term analog storage offers a compact, accurate, and low-power method of implementing temporary local memory that can be useful in adaptive circuit applications. The performance of these cells is characterized by the sampling accuracy and voltage droop that can be achieved with a given level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized in a standard 1.5-/spl mu/m CMOS process using an on-chip current integration technique, focusing specifically on the 1 fA to 1 aA current range. These measurements reveal an accumulation-mode source-drain coupling mechanism that can easily dominate diode leakage under certain bias conditions and may have limited previous designs. A simple rule-of-thumb is offered for avoiding this leakage effect, leading to a novel ultra-low leakage switch topology. A differential storage cell incorporating this new switch achieves an average leakage of 10 aA at room temperature, an 8/spl times/ reduction over past designs. The cell loses one bit of voltage accuracy, 700 /spl mu/V on a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min, respectively. This represents a 15/spl times/ increase in hold time at these voltage accuracies over the lowest leakage cell to date, in only 92% of the area. Since the leakage is independent of amplifier bias, the cell can operate on as little as 10 nW of power. Initial measurements also indicate the switch's leakage decreases with the square of process feature size.

Device sizing for minimum energy operation in subthreshold circuits

Abstract: Digital circuits operating in the subthreshold region provide the minimum energy solution for applications with strict energy constraints. This paper examines the effect of sizing on energy for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18 /spl mu/m test chip is used to compare normal sizing and sizing for minimum V/sub DD/. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm

Abstract: An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the /spl Delta/N model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

High-performance p-type independent-gate FinFETs

Abstract: We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 /spl mu/m, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

Abstract: Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I/sub off/) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (/spl Delta/V/sub to/) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V/sub t/ mismatch shift. This effect can be so severe that I/sub off/ can increase by more than one order of magnitude with respect to its nominal value due only to V/sub to/ mismatch. We further show through experimental results that the V/sub to/ mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I/sub off/ level as for a V/sub to/ mismatch characterized out of the subthreshold regime.

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

Abstract: A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.

A CMOS subbandgap reference circuit with 1-v power supply voltage

Abstract: A CMOS subbandgap reference circuit with 1-V supply voltage is described. To obtain subbandgap reference voltages with a 1-V supply voltage, threshold voltage reduction and subthreshold operation techniques are used. Large /spl Delta/V/sub BE/ (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset. A power-on-reset (POR) circuit is used as startup. This circuit has been implemented using a standard 0.5-/spl mu/m CMOS process, and its size is 940 /spl mu/m/spl times/1160/spl mu/m. The temperature coefficient is 17 ppm from -40/spl deg/C to 125/spl deg/C after resistor trimming and the minimum power supply voltage is 0.95 V. The measured total current consumption is below 10 /spl mu/A and the measured output voltage is 0.631 V at room temperature.

State-preserving vs. non-state-preserving leakage control in caches

Abstract: This paper compares the effectiveness of state-preserving and non-state-preserving techniques for leakage control in caches by comparing drowsy cache and gated-V/sub ss/ for data caches using 70nm technology parameters. To perform the comparison, we introduce "HotLeakage", a new architectural model for subthreshold and gate leakage that explicitly models the effects of temperature, voltage, and parameter variations, and has the ability to recalculate leakage currents dynamically as temperature and voltage change at runtime due to operating conditions, DVS techniques, etc. By comparing drowsy-cache and gated-V/sub ss/ at different L2 latencies and different gate oxide thickness values, we are able to identify a range of operating parameters at which gated-V/sub ss/ is more energy efficient than drowsy-cache, even though gated-V/sub ss/ does not preserve data in cache lines that have been deactivated. We are also able to show potential further benefits of gated-V/sub ss/ if an effective dynamic adaptation technique can be found. These results debunk a fairly widespread belief that state-preserving techniques are inherently superior to non-state-preserving techniques.

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

Abstract: A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.