Showing papers on "Subthreshold conduction published in 2005"

A 180-mV subthreshold FFT processor using a minimum energy design methodology

Abstract: In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage according to A. Chandrakasan et al. (see ibid., vol.27, no.4, p.473-84, Apr. 1992). The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages that are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128-1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18-/spl mu/m CMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz.

Modeling and sizing for minimum energy operation in subthreshold circuits

Abstract: This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Transparent thin-film transistors with zinc indium oxide channel layer

Abstract: High mobility, n-type transparent thin-film transistors (TTFTs) with a zinc indium oxide (ZIO) channel layer are reported. Such devices are highly transparent with ∼85% optical transmission in the visible portion of the electromagnetic spectrum. ZIO TTFTs annealed at 600 °C operate in depletion-mode with threshold voltages −20 to −10V and turn-on voltages ∼3V less than the threshold voltage. These devices have excellent drain current saturation, peak incremental channel mobilities of 45–55cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.8V∕decade. In contrast, ZIO TTFTs annealed at 300 °C typically operate in enhancement-mode with threshold voltages of 0–10V and turn-on voltages 1–2V less than the threshold voltage. These 300 °C devices exhibit excellent drain–current saturation, peak incremental channel mobilities of 10–30cm2V−1s−1, drain current on-to-off ratios of ∼106, and inverse subthreshold slopes of ∼0.3V∕decade. ZIO TTFTs with the channel layer deposited ne...

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

Abstract: In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.

High-performance flexible zinc tin oxide field-effect transistors

Abstract: Flexible transistors were fabricated by sputter deposition of zinc tin oxide (ZTO) onto plasma-enhanced chemical vapor deposition gate dielectrics formed on flexible polyimide substrates with a blanket aluminum gate electrode. The flexible transistors exhibited high on-currents of 1mA, on/off ratios of 106, subthreshold voltage slopes of 1.6V/decade, turn-on voltages of −17V, and mobilities of 14cm2V−1s−1. Capacitance measurements indicate that the threshold voltage and subthreshold slope are primarily influenced by residual doping in the ZTO rather than by defects at the semiconductor/dielectric interface, and are useful for assessing contact resistance.

Full-chip analysis of leakage power under process variations, including spatial correlations

Abstract: In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.

Analysis and mitigation of variability in subthreshold design

Abstract: Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V/sub th/ variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical models against Monte Carlo SPICE simulations and show that they accurately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs.

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Abstract: Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/

A bio-physically inspired silicon neuron

Abstract: The physical principles governing ion flow in biological neurons share interesting similarities to electron flow through the channels of MOSFET transistors. Here, is described a circuit which exploits the similarities better than previous approaches to build an elegant circuit with electrical properties similar to real biological neurons. A two-channel model is discussed including sodium (Na/sup +/) and potassium (K/sup +/). The Na/sup +/ channel uses four transistors and two capacitors. The K/sup +/ channel uses two transistors and one capacitor. One more capacitor simulates the neuron membrane capacitance yielding a total circuit of four capacitors and six transistors. This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology. Voltage and current responses of this circuit correspond well with biology in terms of shape, magnitude, and time.

Subthreshold voltage noise of rat neocortical pyramidal neurones

Abstract: Neurones are noisy elements. Noise arises from both intrinsic and extrinsic sources, and manifests itself as fluctuations in the membrane potential. These fluctuations limit the accuracy of a neurone's output but have also been suggested to play a computational role. We present a detailed study of the amplitude and spectrum of voltage noise recorded at the soma of layer IV–V pyramidal neurones in slices taken from rat neocortex. The dependence of the noise on holding potential, synaptic activity and Na+ conductance is systematically analysed. We demonstrate that voltage noise increases non-linearly as the cell depolarizes (from a standard deviation (s.d.) of 0.19 mV at −75 mV to an s.d. of 0.54 mV at −55 mV). The increase in voltage noise is accompanied by an increase in the cell impedance, due to voltage dependence of Na+ conductance. The impedance increase accounts for the majority (70%) of the voltage noise increase. The increase in voltage noise and impedance is restricted to the low-frequency range (0.2–2 Hz). At the high frequency range (5–100 Hz) the voltage noise is dominated by synaptic activity. In our slice preparation, synaptic noise has little effect on the cell impedance. A minimal model reproduces qualitatively these data. Our results imply that ion channel noise contributes significantly to membrane voltage fluctuations at the subthreshold voltage range, and that Na+ conductance plays a key role in determining the amplitude of this noise by acting as a voltage-dependent amplifier of low-frequency transients.

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

Abstract: We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.

The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Abstract: Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V/sub dd/. However, there is no fundamental reason why designs cannot operate over a much larger voltage range: from full V/sub dd/ to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that, for subthreshold supply voltages, leakage energy becomes dominant, making "just-in-time computation" energy-inefficient at extremely low voltages. Hence, we introduce the existence of a so-called "energy-optimal voltage" which is the voltage at which the application is executed with the highest possible energy efficiency and below which voltage scaling reduces energy efficiency. We derive an analytical model for the energy-optimal voltage and study its trends with technology scaling and different application loads. Second, we compare several different low-power approaches including MTCMOS, standard DVS, and the proposed Insomniac (extended DVS into subthreshold operation). A study of real applications on commercial processors shows that Insomniac provides the best energy efficiency. From these results, we conclude that extending the voltage range below V/sub dd//2 will improve the energy efficiency for many processor designs.

Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs

Abstract: We describe a new drain current model for nanoscale undoped-body symmetric dual-gate MOSFETs based on a fully consistent physical description. The model consists on a single analytic equation that includes both drift and diffusion contributions. It is built on the basis of the potentials at the surface and at the center of the silicon film evaluated at the source and drain ends. The derivation is completely rigorous and is based on a procedure previously enunciated for long-channel bulk SOI MOSFETs. The expression is a continuous description valid for all bias conditions, from subthreshold to strong inversion and from linear to saturation operation. The validity of the model has been ascertained by extensive comparison to exact numerical simulations. The results attest to the excellent accuracy of this formulation.

Device optimization for digital subthreshold logic operation

Abstract: Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.

The state-of-the-art of silicon-on-sapphire CMOS RF switches

Abstract: Silicon-on-Sapphire (SOS) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulating sapphire substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOS FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOS FETs can be stacked in series to withstand high voltages when biased in subthreshold. This work studies the tradeoffs of SOS RF switch design and compares SOS against other technologies such as GaAs and Si-based SOI. Also presented is a high power SP6T switch with insertion loss of 0.6 dB at 2 GHz and isolation of 40 dB at 2 GHz. The presented switch has the highest linearity reported to date of any SP6T switch with a P1dB of 20 W and OIP3 of <+70 dBm.

Contrast Adaptation in Subthreshold and Spiking Responses of Mammalian Y-Type Retinal Ganglion Cells

Abstract: Retinal ganglion cells adapt their responses to the amplitude of fluctuations around the mean light level, or the “contrast.” But, in mammalian retina, it is not known whether adaptation arises exclusively at the level of synaptic inputs or whether there is also adaptation in the process of ganglion cell spike generation. Here, we made intracellular recordings from guinea pig Y-type ganglion cells and quantified changes in contrast sensitivity (gain) using a linear-nonlinear analysis. This analysis allowed us to measure adaptation in the presence of nonlinearities, such as the spike threshold, and to compare adaptation in subthreshold and spiking responses. At high contrast (0.30), relative to low contrast (0.10), gain reduced to 0.82 ± 0.016 (mean ± SEM) for the subthreshold response and to 0.61 ± 0.011 for the spiking response. Thus, there was an apparent reduction in gain between the subthreshold and spiking response of 0.74 ± 0.013. Control experiments suggested that the above effects could not be explained by an artifact of the intracellular recording conditions: extracellular recordings showed a gain change of 0.58 ± 0.022. For intracellular recordings, negative current reduced the spike output but did not affect the gain change in the subthreshold response: 0.80 ± 0.051. Thus, adaptation in the subthreshold response did not require spike-dependent conductances. We conclude that the contrast-dependent gain change in the spiking response can be explained by both a synaptic mechanism, as reflected by responses in the subthreshold potential, and an intrinsic mechanism in the ganglion cell related to spike generation.

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

Abstract: Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit. In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping profile, and operating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures.

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Abstract: Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In this paper, we demonstrate that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area, ii) increase the utility of transistors, while iii) maintaining acceptable CPI efficiency. We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM and is currently being tested.

Image-sensing apparatus

Abstract: In a solid-state image-sensing device, when image sensing is performed, in each pixel, MOS transistors T 1 and T 5 are turned on and a MOS transistor T 6 is turned off so that a MOS transistor T 2 operates in a subthreshold region. When resetting is preformed, in each pixel, the MOS transistors T 1 and T 5 are turned off and the MOS transistor T 6 is turned on so that the gate voltage of the MOS transistor T 2 is kept constant. In this state, the MOS transistor T 2 is brought first into a conducting state and then, by turning a signal φVPS to a high level, into a cut-off state. This permits a signal proportional to the threshold value of the MOS transistor T 2 to be output as compensation data.

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

Abstract: Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

Abstract: A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.

Leakage power analysis and reduction: models, estimation and tools

Abstract: The high leakage current in the nanometre regime is becoming a significant proportion of power dissipation in CMOS circuits as threshold voltage, channel length and gate oxide thickness are scaled. Consequently, the identification and estimation of different leakage currents are very important in designing low power circuits. In the paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modelling of the different leakage currents in nanoscaled bulk CMOS devices is demonstrated. Different leakage currents are modelled based on the device geometry, 2-D doping profile and operating temperature. A circuit level model of subthreshold, junction band-to-band tunnelling (BTBT) and gate leakage is described. The presented model includes the impact of quantum mechanical behaviour of substrate electrons on the circuit leakage. Using the compact current model, a transistor has been modelled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25 nm effective length) at room and elevated temperatures.

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

Abstract: The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.

A surface-potential-based high-voltage compact LDMOS transistor model

Abstract: In this paper, a surface potential-based compact model is described for high-voltage LDMOS transistors. This model combines the low-voltage MOS region with the high-voltage drift region of an LDMOS transistor. The model includes the effect of the gate extending over the drift region as well as its temperature behavior and geometry scaling. In contrast to subcircuit models, the model has no internal node, since the so-called internal drain voltage is explicitly expressed in terms of the external terminal voltages. By use of an explicit formulation of the surface potential, the dc model thus combines the benefits of short computation times and robustness with accuracy. A comparison with dc measurements shows that the dc model provides an accurate description in all regimes of operation, ranging from subthreshold to super-threshold. In addition, a nodal charge model is derived, to account for the time-dependent behavior of the device. Capacitances obtained from high-frequency measurements show a good agreement with those obtained from the nodal charge model.

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

Abstract: This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for super-threshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows /spl sim/2.5/spl times/ improvement in throughput at iso-power compared to a conventional design.

Performance of 2 nm gate length carbon nanotube field-effect transistors with source∕drain underlaps

Abstract: The performance of coaxially gated, zero-Schottky-barrier, carbon nanotube field-effect transistors is investigated for gate lengths down to 2 nm with source and drain underlaps. Such devices can have nearly ideal subthreshold slopes of ∼63mV∕dec and maximum on∕off current ratios of 2.2×106 assuming 0.0–0.4 volt swing. The leakage mechanism is a combination of both intra-band and inter-band tunneling. For a 30 nm long carbon nanotube (CNT) with a 2 nm gate, Cg=3.13aF, the intrinsic switching time, τs=CgVDD∕ION, is 370 fs, and the intrinsic cut-off frequency defined by fT=gm∕(2πCg) is 1.6 THz. The ambipolar leakage current is suppressed by Coulomb blockade. Calculations are performed using a π-bond model and a self-consistent solution of the nonequilibrium Green function equations and Poisson’s equation.

Wide-linear-range subthreshold OTA for low-power, low-Voltage, and low-frequency applications

Abstract: We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-/spl mu/m, CMOS process. The power consumption of the OTA remains below 1 /spl mu/W for biasing currents in the range between 1-200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors.

Low-power low-voltage reference using peaking current mirror circuit

Abstract: A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.

Challenges and design choices in nanoscale CMOS

Abstract: The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits

Abstract: An accurate and efficient stacking effect macro-model for leakage power in sub-100 nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more significant compared to dynamic power when technology scaling down below 100 nm. Consequently, fast and accurate leakage power estimation models, which are strongly dependent on precise modeling of the stacking effect on subthreshold leakage and gate leakage, are vital for evaluating optimizations. In this work, making use of the interactions between subthreshold leakage and gate leakage, we focus our attention on analyzing the effects of transistor stacking on gate leakage between the channel and the gate and that between the drain/source and the gate. The contribution of the latter has been largely ignored in prior work, while our work shows that it is an important factor. Based on the stacking effect analysis, we have proposed a new best input vector to reduce the total leakage power; and an efficient and accurate leakage power estimation macro-model which achieves a mean error of 3.1% when compared to HSPICE.