Showing papers on "Subthreshold conduction published in 2009"
TL;DR: Experimental data is presented indicating that cortical neuron morphology relative to electric fields and cortical cell type are factors in determining sensitivity to sub- and supra-threshold brain stimulation.
584 citations
TL;DR: A differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability and provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC).
Abstract: Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of 6T).
456 citations
TL;DR: Results suggest that subthreshold eating disorders are more prevalent than threshold eating disorders and are associated with marked impairment and diagnostic crossover was most likely for these disorders.
Abstract: The authors examined the natural history of threshold, subthreshold, and partial eating disorders in a community sample of 496 adolescent girls who completed annual diagnostic interviews over an 8-year period. Lifetime prevalence by age 20 years was 0.6% and 0.6% for threshold and subthreshold anorexia nervosa (AN), 1.6% and 6.1% for threshold and subthreshold bulimia nervosa (BN), 1.0% and 4.6% for threshold and subthreshold binge-eating disorder (BED), and 4.4% for purging disorder (PD). Overall, 12% of adolescents experienced some form of eating disorder. Subthreshold BN and BED and threshold PD were associated with elevated treatment, impairment, and distress. Peak age of onset was 17-18 years for BN and BED and 18-20 years for PD. Average episode duration in months was 3.9 for BN and BED and 5.1 for PD. One-year recovery rates ranged from 91% to 96%. Relapse rates were 41% for BN, 33% for BED, and 5% for PD. For BN and BED, subthreshold cases often progressed to threshold cases and diagnostic crossover was most likely for these disorders. Results suggest that subthreshold eating disorders are more prevalent than threshold eating disorders and are associated with marked impairment.
420 citations
TL;DR: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology and would be suitable for use in subthreshold-operated, power-aware LSIs.
Abstract: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
346 citations
TL;DR: In this paper, the authors proposed n-and p-type tunnel field effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer, which exhibit very small subthreshold swings, as well as low threshold voltages.
Abstract: In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~104 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.
306 citations
TL;DR: A 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV, and a switched capacitor DC-DC converter is integrated on-chip, achieving above 75% efficiency.
Abstract: Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.
293 citations
TL;DR: Many subthreshold conditions have predictive validity as they may represent precursors for full syndrome disorders and may represent good targets for preventive interventions.
Abstract: Since the advent of well-specified psychiatric diagnostic systems, such as the DSM’s 1980 3rd revision, reliability of diagnoses has greatly improved as has the precision of prevalence rates. These systems employ specific thresholds for determining ‘caseness’ but, recently, interest in studying subthreshold conditions (i.e., slightly below the threshold) has increased (Pincus, McQueen, & Elinson, 2003). This work is especially important because subthreshold conditions are common (Lewinsohn, Shankman, Gau & Klein, 2004), and are associated with functional impairment (Kessler, Zhao, Blazer, & Swartz, 1997) Studying subthreshold conditions can help determine whether full syndromes (FS) are qualitatively different from conditions below diagnostic thresholds or whether they are merely more severe forms on a continuum (Flett, Vredenburg, & Krames, 1997; Lewinsohn, Solomon, Steeley, & Zeiss, 2000a).
Among subthreshold conditions, subthreshold depression has been studied the most extensively. Subthreshold depressive conditions, such as minor depression or Brief Recurrent Depression, have been associated with significant impairment (Gotlib, Lewinsohn, & Seeley, 1995; Kessler et al., 1997), and increased treatment utilization (Judd, Paulus, Wells & Rapaport, 1996). Similar results have been found for subthreshold bipolar (Lewinsohn, Klein & Seeley, 2000b), anxiety (Batelaan, De Graaf, Van Balkom, Vollebergh, & Beekman, 2007), and alcohol and substance use disorders (Pollock & Martin, 1999).
The clinical significance and validity of subthreshold conditions can be addressed with several different methods (Robins & Guze, 1970). Cross-sectional studies can establish the prevalence of subthreshold conditions and whether they are associated with impairment. Family studies can elucidate whether FS and subthreshold conditions are associated with qualitatively distinct familial liabilities. Using data from the Oregon Adolescent Depression Project (OADP), we have begun to examine these questions (Lewinsohn et al., 2004; Shankman, Klein, Lewinsohn, Seeley & Small, 2008). In this paper, we will extend these studies by examining the prospective course of subthreshold conditions. Specifically, we will examine whether subthreshold conditions are likely to develop or escalate into FS disorders.
Subthreshold depression (Fergusson, Horwood, Ridder & Beautrais, 2005; Lewinsohn et al., 2000a) bipolar disorder (Lewinsohn et al, 2000b; Regeer et al., 2006) and anxiety disorder (Merikangas et al., 2003) have been shown to escalate into the FS condition over time. These and similar studies have led many to argue that subthreshold conditions may be precursors of the FS (Eaton, Badawi & Melton, 1995, Pincus et al., 2003).
Most subthreshold studies only examine whether a single subthreshold condition is likely to develop into the FS form of that disorder over time (i.e., homotypic development). Equally important, however, is whether subthreshold conditions predict the development of other FS disorders over time (i.e., heterotypic development), as heterotypic developments can elucidate whether subthreshold conditions are precursors to broad classes of psychopathologies. With the possible exception of MDD and bipolar disorder, heterotypic developments have been largely ignored in the subthreshold literature (Lewinsohn et al., 2000b; Regeer et al., 2006).
We predict that, in addition to homotypic escalation, several subthreshold conditions will develop into heterotypic FS disorders, as there is substantial comorbidity and familial co-aggregation among subthreshold and FS conditions (Angst, Merikangas & Preisig, 1997; Lewinsohn et al., 2004; Shankman et al., 2008). Given the phenotypic and genotypic clustering of psychopathologies into broad classes of internalizing and externalizing disorders (Kendler, Prescott, Myers, & Neale, 2003; Krueger & Markon, 2006), we expect that subthreshold internalizing disorders such as depression and anxiety will escalate into FS forms of each other (Fergusson et al., 2005), and subthreshold externalizing disorders such as alcohol, substance, and conduct /antisocial personality disorder (ASPD) will escalate into FS forms of one another (Hicks et al., 2007). It is also possible that externalizing subthreshold conditions may escalate into internalizing conditions given recent support (Kim-Cohen et al., 2003), though these findings are less likely than within class escalation.
272 citations
TL;DR: In this paper, a generic analytical model for the current-voltage characteristics of organic thin-film transistors (OTFTs) is derived, and a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed.
Abstract: A generic analytical model for the current-voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation-linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current-voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.
207 citations
TL;DR: In this article, a metal-oxide charge injection layer at the contact/semiconductor interface of organic field-effect transistors (OFETs) was proposed to improve the threshold voltage and sub-threshold slope.
Abstract: The charge injection efficiency of organic field-effect transistors (OFETs) is found to be a critical factor determining the subthreshold characteristics of these devices. OFETs fabricated using a wide band gap organic semiconductor and gold source/drain contacts display large threshold voltage and poor subthreshold characteristics. Insertion of a metal-oxide charge injection layer at the contact/semiconductor interface lower the injection barrier height, resulting in marked improvements in threshold voltage and subthreshold slope and strong suppression of the short-channel effect. The improved subthreshold characteristics are attributed to enhanced charge injection and the consequent promotion of charge accumulation.
166 citations
TL;DR: This paper proposes a new general-purpose sensor processor architecture, which is called the Subliminal Processor, optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization.
Abstract: Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point (Knin)- However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-mum technology, which is sufficiently low to operate at Vmin . Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and Vmin across die to verify our analysis of adaptive tuning of the clock frequency and Vmin for optimal energy efficiency.
157 citations
TL;DR: In this article, a lowvoltage, high-performance amorphous indium gallium zinc oxide n-channel thin-film transistors fabricated using 100nm-thick Al2O3 grown by atomic layer deposition as the gate dielectric layer are presented.
Abstract: We report on low-voltage, high-performance amorphous indium gallium zinc oxide n-channel thin-film transistors fabricated using 100-nm-thick Al2O3 grown by atomic layer deposition as the gate dielectric layer. The Al2O3 gate dielectric shows very small current densities and has a capacitance density of 81±1 nF/cm2. Due to a very small contact resistance, transistors with channel lengths ranging from 100 μm down to 5 μm yield a channel-independent, field-effect mobility of 8±1 cm2/V s, subthreshold slopes of 0.1±0.01 V/decade, low threshold voltages of 0.4±0.1 V, and high on-off current ratios up to 6×107 (W/L=400/5 μm) at 5 V.
TL;DR: In this article, a lateral strained double-gate TFET (SDGTFET) is presented, which has a higher on-current, low leakage, low threshold voltage, excellent sub-threshold slope, and good short channel effects.
Abstract: Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.
TL;DR: This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V, enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability.
Abstract: In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access.
TL;DR: In this article, the role of the In atoms is to enhance the mobility and to shift the threshold voltage negatively, while the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface.
Abstract: Thin film transistors with a channel of Zn–In–Sn–O were fabricated via a combinatorial rf sputtering method. It was found that the role of the In atoms is to enhance the mobility and to shift the threshold voltage (Vth) negatively. On the other hand, the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface. The optimized transistor was obtained at a compositional ratio of Zn:In:Sn=40:20:40, which exhibited an excellent subthreshold gate swing of 0.12 V/decade, Vth of −0.4 V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 24.6 cm2/V s.
TL;DR: In this paper, the surrounding field effect in a multi-mesa channel (MMC) with an AlGaN/GaN structure, in which a periodic trench structure is fabricated directly under a gate electrode, was successfully observed.
Abstract: The surrounding-field effect in a multi-mesa-channel (MMC) with an AlGaN/GaN structure, in which a periodic trench structure is fabricated directly under a gate electrode, was successfully observed. This effect resulted in a shallower threshold voltage, a smaller subthreshold slope, and a higher current drivability of a high electron mobility transistor (HEMT) than those of a standard planar-type HEMT. In addition, the MMC HEMT showed a low knee voltage, even with a wide spacing between the gate and drain electrodes. Excellent current stability in the saturation region of the MMC HEMT, probably due to the effective radiation of heat from both mesa sides of the channel, was also observed. Both planar and MMC HEMTs showed similar breakdown voltages under off-state operation, indicating no significant degradation in the breakdown characteristics of AlGaN/GaN HEMTs with a periodic trench structure in the gate region.
TL;DR: This paper describes a motion estimation engine fabricated in 65 nm CMOS, targeted for special-purpose on-die acceleration of sum of absolute difference (SAD) computation in real-time video encoding workloads on power-constrained mobile microprocessors.
Abstract: This paper describes a motion estimation engine fabricated in 65 nm CMOS, targeted for special-purpose on-die acceleration of sum of absolute difference (SAD) computation in real-time video encoding workloads on power-constrained mobile microprocessors. Four-way speculative difference computation using dual 4:2 compressors, optimal reuse of sum XOR min-terms in static 4:2 compressor carry gates, distributed accumulation of input carries for efficient negation and robust ultra-low voltage optimized circuits enable peak SAD efficiency of 12.8 macro-block SADs/nJ within a dense layout occupying 0.089 mm2 while achieving: (i) scalable performance up to 2.4 GHz, 82 mW measured at 1.4 V, 50degC , (ii) deep subthreshold operation measured at 230 mV while operating down to 4.3 MHz and consuming 14.4 muW , (iii) maximum energy efficiency of 411 GOPS/Watt by operating at 320 mV, 23 MHz and consuming 56 muW (9.6x higher efficiency than nominal 1.2 V operation), (iv) 20% higher energy efficiency for up-conversion of ultra-low voltage signals using a two-stage cascaded split-output level shifter, and (v) tolerance of up to plusmn2x process and temperature induced performance variation using supply voltage compensation of plusmn50 mV.
Abstract: A 6-bit highly digital flash ADC is implemented in a 0.18 mum CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling switch employs voltage boosting, stacking and feedback to reduce leakage. Common-mode rejection is implemented digitally via an IIR filter. The minimum FOM of the ADC is 125 fJ/conversion-step at a 0.4 V supply, where it achieves an ENOB of 5.05 at 400 kS/s. The clocked comparators' switching thresholds are adjusted through a combination of device sizing and stacking. A quadratic relationship between the amount of device stacking and the strength of an input network in the subthreshold regime is derived, demonstrating an advantage of stacking over device width scaling to adjust comparator thresholds.
TL;DR: In this article, a parameter extraction methodology and a verification of a generic analytical model and a thin-film transistor (TFT) compact dc model for the currentvoltage characteristics of organic TFTs are presented.
Abstract: A parameter extraction methodology and a verification of a generic analytical model and a thin-film transistor (TFT) compact dc model for the current-voltage characteristics of organic TFTs are presented. The verification shows that the proposed models meet the requirements for compact modeling and for computer circuit simulators. The models are fully symmetrical, and the TFT compact dc model is validated in all regimes of operation-linear and saturation above threshold, subthreshold, and reverse biasing. Suitable characterization techniques for parameter extraction of mobility, threshold voltage, and contact resistance are provided. Approaches are elaborated for the essential practical feature of upgradability and reducibility of the TFT compact dc model, allowing for easier implementation and modification, as well as separation of characterization techniques.
19 Aug 2009
TL;DR: This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade and proposes a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow.
Abstract: The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing
TL;DR: It is shown that an optimal amplitude of the high-frequency driving enhances the response of coupled excited neurons to a subthreshold low-frequency input, and the chemical synaptic coupling is more efficient than the well-known electrical coupling (gap junction).
Abstract: The response of three coupled FitzHugh–Nagumo neurons, under high-frequency driving, to a subthreshold low-frequency signal is investigated. We show that an optimal amplitude of the high-frequency driving enhances the response of coupled excited neurons to a subthreshold low-frequency input, and the chemical synaptic coupling is more efficient than the well-known electrical coupling (gap junction), especially when the coupled neurons are near the canard regime, for local signal input, i.e., only one of the three neurons is subject to a low-frequency signal. The influence of additive noise and the interplay between vibrational and stochastic resonance are also analyzed.
TL;DR: Two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented.
Abstract: In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.
TL;DR: In this paper, the fabrication and electrical properties of amorphous (α-)InGaZnO4 thin-film transistors deposited on cellulose paper by sputtering at room temperature were reported.
Abstract: We report on the fabrication and the electrical properties of amorphous (α-)InGaZnO4 thin-film transistors deposited on cellulose paper by sputtering at room temperature. The 150-μm-thick paper was used as both a gate dielectric and a substrate for device structural support. The transistors on paper were patterned by lithography and operated in enhancement mode with a threshold voltage of 3.75 V, and exhibited saturation mobility, subthreshold gate-voltage swing, and drain current on-to-off ratio of ∼35 cm2 V−1 s−1, 2.4 V decade−1, and ∼104, respectively. These results verify that simple cellulose paper is a good gate dielectric as well as a low-cost substrate for flexible electronic devices such as paper-based displays.
TL;DR: The dependence of the subthreshold-swing degradation on fin width is reported for irradiated 100-nm-gate-length, fully depleted n-channel FinFETs in this paper.
Abstract: The dependence of the subthreshold-swing (SS) degradation on fin width is reported for irradiated 100-nm-gate- length, fully depleted n -channel FinFETs. The wider the fin is, the greater the radiation-induced SS degradation. The higher tolerance to radiation-induced charge for the narrower FinFETs is attributed to the additional lateral gate control over the body potential. The irradiation and room temperature annealing results suggest that the SS increase for wider FinFETs is due primarily to nonuniform trapped charge in the buried oxide (BOX). The subthreshold characteristics of FinFETs with two fins are more likely to exhibit a nonuniform subthreshold slope (NUSS), resulting from fin-to-fin variability, than FinFETs with 20 fins, where the corresponding Id -V gs curve is the composite of the 20 individual Id-V gs curves.
IBM1
TL;DR: In this paper, a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented.
Abstract: We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).
TL;DR: In this article, the authors show that the maximum SNR is obtained when the device is operated in the sub-threshold regime, where the conductivity of the contact regions can be increased using a conventional back gate.
Abstract: The signal-to-noise ratio (SNR) for real-time biosensing with liquid-gated carbon nanotube transistors is crucial for exploring the limits of their sensitivity, but has not been studied thus far. Although biosensing is often performed at high transconductance where the device displays the largest gate response, here we show that the maximum SNR is actually obtained when the device is operated in the subthreshold regime. In the ON-state, additional contributions to the noise can lead to a reduction of the SNR by up to a factor of 5. For devices with passivated contact regions, the SNR in ON-state is even further reduced than for bare devices. We show that when the conductivity of the contact regions can be increased using a conventional back gate, the SNR in the ON-state can be improved. The results presented here demonstrate that biosensing experiments are best performed in the subthreshold regime for optimal SNR.
24 May 2009
TL;DR: A ring oscillator-based CMOS temperature sensor with nano-watt power consumption is presented for RFID applications that exploits the temperature dependence of the threshold voltage and carrier mobility of MOS transistors that affect the frequency of a ring oscillators.
Abstract: In this paper, a ring oscillator-based CMOS temperature sensor with nano-watt power consumption is presented for RFID applications. Unlike conventional temperature sensors based on bandgap reference and ADC that consume large amount of power, the proposed sensor exploits the temperature dependence of the threshold voltage and carrier mobility of MOS transistors that affect the frequency of a ring oscillator. In order to maximize the temperature sensitivity and dynamic range, a supply voltage of 0.3V is used, which allows the oscillator to operate in subthreshold, near-threshold and above threshold region under different temperature conditions. In order to handle process variation, the frequency of the oscillator can be digitally trimmed by both a capacitor bank and stacked transistors. Measured data from 0.13-µm CMOS test chips indicate that the proposed temperature sensor has a resolution of 0.4°C/LSB with a 10-bit digital output code over a temperature range of 8°C to 85°C. At 10Hz of sampling frequency, the proposed sensor consumes 95nW and occupies 0.04mm2.
TL;DR: In this paper, small-molecule p-and n-type organic semiconductors are combined with the highly water repellent fluoropolymer Cytop™ as the gate dielectric.
Abstract: We present results on small-molecule p- and n-type organic semiconductors in combination with the highly water repellent fluoropolymer Cytop™ as the gate dielectric. Using pentacene and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylicdiimide (PTCDI-C13), we fabricated complementary inverters of high electrical quality and stability that are almost unaffected by repeated gate bias stress. The combined p- and n-type field-effect transistors show nearly ideal characteristics, very small hysteresis, and similar saturation mobility (∼0.2 cm2/V s). Particularly PTCDI-C13 thin-film transistors exhibit a remarkable performance in the subthreshold regime if chromium is used as contact material for electron injection: a near zero onset and a subthreshold swing as low as 0.6 V/decade.
TL;DR: In this article, a unified charge control expression applicable to both subthreshold regions and strong inversion regions is determined, while the parasitic channel effect in AlGaN layer is also taken into account.
Abstract: A set of explicit analytical solutions to the charge concentration, current, and capacitance characteristics of AlGaN/GaN MODFETs in different working regions is developed. First, a unified charge control expression applicable to both subthreshold regions and strong inversion regions is determined, while the parasitic channel effect in AlGaN layer is also taken into account. The onset voltage for this parasitic channel is estimated for the first time. Based on the improved charge control model, the current (I ds), the transconductance (gm), and the output conductance (gd) are given explicitly and are applicable in a wide bias range. Moreover, the gate-to-source capacitance (C gs ) and gate-to-drain capacitance (C gd) have been obtained analytically under various applied biases, and, consequently, the cutoff frequency can be predicted. The present model shows good agreement with the experimental data and is useful for microwave circuit design and analysis.
TL;DR: In this article, an analytical model has been developed to describe the photosensitive behavior of organic phototransistors based on a composite of P3HT and TiO2 nanoparticles, which show high photosensitivity, fast response, and stable performance under both visible and ultraviolet light illumination.
Abstract: Organic phototransistors based on a composite of P3HT and TiO2 nanoparticles have been fabricated, which show high photosensitivity, fast response, and stable performance under both visible and ultraviolet light illumination, and thus they are promising for applications as low cost photosensors. The transfer characteristic of each device exhibits a parallel shift to a positive gate voltage under light illumination, and the channel current increases up to three orders of magnitude in the subthreshold region. The shift in the threshold voltage of the device has a nonlinear relationship with light intensity, which can be attributed to the accumulation of electrons in the embedded TiO2 nanoparticles. It has been found that the device is extremely sensitive to weak light due to an integration effect. The relationship between the threshold voltage change and the intensity of light illumination can be fitted with a power law. An analytical model has been developed to describe the photosensitive behavior of the d...
TL;DR: In this article, the authors describe the fabrication, electrical and electrochemical characterization of silicon nanowire arrays, which were processed in a top-down approach using combined nanoimprint lithography and wet chemical etching.
Abstract: We describe the fabrication, electrical and electrochemical characterization of silicon nanowire arrays, which were processed in a top-down approach using combined nanoimprint lithography and wet chemical etching. We used the top silicon layer as contact line and observed an influence of implantation and subsequent annealing of these lines to the device performance. In addition we found a subthreshold slope dependence on wire size. When operated in a liquid environment, wires can be utilized as pH sensors. We characterized the pH sensitivity in the linear range and in the subthreshold operation regime. As a first proof-of-principle experiment for the later use of the sensors in bioassays, we monitored the buildup ofpolyelectrolyte multilayers on the wire surface.