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Showing papers on "Subthreshold conduction published in 2010"


Journal ArticleDOI
22 Jan 2010
TL;DR: In this paper, the authors define and explore near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors.
Abstract: Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

767 citations


01 Jan 2010
TL;DR: The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described.
Abstract: Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favor- able performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

695 citations


Journal ArticleDOI
TL;DR: It is demonstrated that the sensitivity of NW-FET sensors can be exponentially enhanced in the subthreshold regime where the gating effect of molecules bound on a surface is the most effective due to the reduced screening of carriers in NWs.
Abstract: Nanowire field-effect transistors (NW-FETs) are emerging as powerful sensors for detection of chemical/biological species with various attractive features including high sensitivity and direct electrical readout. Yet to date there have been limited systematic studies addressing how the fundamental factors of devices affect their sensitivity. Here we demonstrate that the sensitivity of NW-FET sensors can be exponentially enhanced in the subthreshold regime where the gating effect of molecules bound on a surface is the most effective due to the reduced screening of carriers in NWs. This principle is exemplified in both pH and protein sensing experiments where the operational mode of NW-FET biosensors was tuned by electrolyte gating. The lowest charge detectable by NW-FET sensors working under different operational modes is also estimated. Our work shows that optimization of NW-FET structure and operating conditions can provide significant enhancement and fundamental understanding for the sensitivity limits ...

529 citations


Journal ArticleDOI
22 Jan 2010
TL;DR: This paper explores how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point, and introduces a pass-transistor based logic family that excels in this operational region.
Abstract: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

391 citations


Journal ArticleDOI
TL;DR: It is shown that a single arsenic dopant atom dramatically affects the off-state room-temperature behaviour of a short-channel field-effect transistor fabricated with standard microelectronics processes, and suggests a path to incorporating quantum functionalities into silicon CMOS devices through manipulation of single donor orbitals.
Abstract: A single dopant atom can dominate the subthreshold behaviour of a field-effect transistor, and this effect is enhanced if the atom is located near a dielectric.

250 citations


Journal ArticleDOI
TL;DR: In this article, the improvement of sub-threshold slope due to impact ionization is compared between standard inversion-mode multigate silicon nanowire transistors and junctionless transistors.
Abstract: The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope.

220 citations


Proceedings ArticleDOI
19 Jun 2010
TL;DR: In this paper, a spin-torque transfer magnetoresistive RAM (STT-MRAM) based implementation of an eight-core Sun Niagara-like CMT processor is presented.
Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

213 citations


Journal ArticleDOI
TL;DR: An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 μm CMOS process for passive RFID food monitoring applications, illustrating proper sensing operation for passiveRFID applications.
Abstract: An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 μm CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) signals can be obtained through proper transistor sizing. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 333 samples/s and achieves an inaccuracy of + 1/-0.8°C from - 10°C to 30°C after calibration. The sensor is embedded inside the fabricated passive UHF RFID tag. Measurement of the sensor performance at the system level is also carried out, illustrating proper sensing operation for passive RFID applications.

192 citations


Journal ArticleDOI
TL;DR: In this paper, a systematic study of GaN-based heterostructure field effect transistors with an insulating carbon-doped GaN back barrier for high-voltage operation is presented.
Abstract: A systematic study of GaN-based heterostructure field-effect transistors with an insulating carbon-doped GaN back barrier for high-voltage operation is presented. The impact of variations of carbon doping concentration, GaN channel thickness, and substrates is evaluated. Tradeoff considerations in on-state resistance versus current collapse are addressed. Suppression of the off-state subthreshold drain-leakage currents enables a breakdown voltage enhancement of over 1000 V with a low on-state resistance. Devices with a 5-μm gate-drain separation on semi-insulating SiC and a 7-μm gate-drain separation on n-SiC exhibit 938 V and 0.39 mΩ·cm2 and 942 V and 0.39 m Ω·cmcm2, respectively. A power device figure of merit of ~ 2.3 × 109 V2/Ω·cm2 was calculated for these devices.

191 citations


Journal ArticleDOI
TL;DR: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature and previously proposed rule of thumbs to evaluate minimum voltage are theoretically justified.
Abstract: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.

176 citations


Journal ArticleDOI
TL;DR: The study lends credence to the clinical significance of subthreshold PTSD and emphasizes that associated impairment may be significant and longstanding and confirms clinical differences between subth threshold and full PTSD.

Journal ArticleDOI
TL;DR: This paper investigates the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications and shows improvements in gate- and channel-engineered devices.
Abstract: The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.

Journal ArticleDOI
TL;DR: A novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels and does not require a static current flow and can therefore offer considerable static power savings is proposed.
Abstract: In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.

Journal ArticleDOI
TL;DR: In this paper, a 150-nm gate enhancement-mode InAlN/Aln/GaN high-electron-mobility transistors are demonstrated on SiC substrates using plasma-based gate-recess etch.
Abstract: Having a drain current density of 1.9 A/mm, a peak extrinsic transconductance of 800 mS/mm (the highest reported in III-nitride transistors), ft/fmax of 70/105 GHz, and Vbr of 29 V, 150-nm-gate enhancement-mode InAlN/AlN/GaN high-electron-mobility transistors are demonstrated on SiC substrates using plasma-based gate-recess etch. The possible plasma-induced damage in the gate region was investigated using interface-trap states extracted from temperature-dependent subthreshold slopes.

Journal ArticleDOI
TL;DR: In this paper, a comprehensive physics-based surface potential and drain current model for the negative capacitance (NC) field effect transistor (FET) is presented, which is aimed to evaluate the potentiality of such transistors for low power switching applications.
Abstract: In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance (NC) region could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S <; 60mV/dec). In this paper, a comprehensive physics-based surface potential and a drain current model for the NC field-effect transistor are reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. This paper also sheds light on how operation in the NC region can be experimentally detected.

Journal ArticleDOI
TL;DR: In this paper, GaN-based high-electron mobility transistors with planar multiple grating field plates (MGFPs) for high-voltage operation are described and a synergy effect with additional electron channel confinement by using a heterojunction AlGaN back barrier (BB) is demonstrated.
Abstract: GaN-based high-electron mobility transistors with planar multiple grating field plates (MGFPs) for high-voltage operation are described. A synergy effect with additional electron channel confinement by using a heterojunction AlGaN back barrier (BB) is demonstrated. Suppression of the OFF-state subthreshold gate and drain leakage currents enables breakdown voltage enhancement over 700 V and a low ON-state resistance of 0.68 mΩ × cm2. Such devices have a minor tradeoff in ON-state resistance, lag factor, maximum oscillation frequency, and cutoff frequency. A systematic study of the MGFP design and the effect of Al composition in the BB is described. Physics-based device simulation results give insight into electric field distribution and charge carrier concentration, depending on the field plate design.

Journal ArticleDOI
TL;DR: This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage with robust results from a 130-nm test chip.
Abstract: This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage. Measured results from a 130-nm test chip show robust conversion from 188 mV to 1.2 V with no intermediate supplies required. A combination of circuit methods makes the converter robust to the large variations in the current characteristics of subthreshold circuits. To support dynamic voltage scaling, the level converter can upconvert an input at any voltage within this range to 1.2 V.

Journal ArticleDOI
TL;DR: In this paper, an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor with a high-k dielectric layer on a glass substrate is presented.
Abstract: In this letter, we report the fabrication of an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor with a high-k dielectric layer on a glass substrate. The room-temperature-deposited a-IGZO channel with Ta2O5 exhibits the following operating characteristics: a threshold voltage of 0.25 V, a drain-source current on/off ratio of 105, a subthreshold gate voltage swing of 0.61 V/decade, and a high field-effect mobility of 61.5 cm2/V·s; these characteristics make it suitable for use as a switching transistor and in low-power applications.

Journal ArticleDOI
01 Dec 2010
TL;DR: Asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell.
Abstract: In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

Journal ArticleDOI
22 Jan 2010
TL;DR: This paper presents a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points.
Abstract: Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

Journal ArticleDOI
Bin Deng1, Jiang Wang, Xile Wei, K.M. Tsang, Wai-Lok Chan 
09 Mar 2010-Chaos
TL;DR: It is shown that optimal amplitude of high-frequency driving enhances the response of neuron populations to a subthreshold low-frequency input and the optimal amplitude dependences on the connection among the neurons.
Abstract: In this paper different topologies of populations of FitzHugh–Nagumo neurons have been introduce to investigate the effect of high-frequency driving on the response of neuron populations to a subthreshold low-frequency signal. We show that optimal amplitude of high-frequency driving enhances the response of neuron populations to a subthreshold low-frequency input and the optimal amplitude dependences on the connection among the neurons. By analyzing several kinds of topology (i.e., random and small world) different behaviors have been observed. Several topologies behave in an optimal way with respect to the range of low-frequency amplitude leading to an improvement in the stimulus response coherence, while others with respect to the maximum values of the performance index. However, the best results in terms of both the suitable amplitude of high-frequency driving and high stimulus response coherence have been obtained when the neurons have been connected in a small-world topology.

Journal ArticleDOI
TL;DR: In the absence of light, the polarity of bias stress controls the magnitude and direction of the threshold voltage shift (ΔVT), while under light stress, VT consistently shifts negatively as mentioned in this paper.
Abstract: Electrical bias and light stressing followed by natural recovery of amorphous hafnium-indium-zinc-oxide (HIZO) thin film transistors with a silicon oxide/nitride dielectric stack reveals defect density changes, charge trapping and persistent photoconductivity (PPC) In the absence of light, the polarity of bias stress controls the magnitude and direction of the threshold voltage shift (ΔVT), while under light stress, VT consistently shifts negatively In all cases, there was no significant change in field-effect mobility Light stress gives rise to a PPC with wavelength-dependent recovery on time scale of days We observe that the PPC becomes more pronounced at shorter wavelengths

Journal ArticleDOI
TL;DR: In this article, the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on sub-threshold circuit performance for 32 nm bulk CMOS.
Abstract: Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

Journal ArticleDOI
TL;DR: An asynchronous design approach using critical-path replica to generate completion signals of combinational logic blocks and classical four-phase handshaking for communication between pipeline flip-flops to address challenges in subthreshold operation.
Abstract: Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely sensitive to PVT variations under subthreshold operation. Hence, large delay margin is required for successful operation of conventional synchronous designs. Since leakage energy contributes to a substantial portion of total energy dissipation in subthreshold operation, the leakage energy dissipated for the required delay margin degrades energy efficiency significantly. In addition, even small intra-die variations result in large clock skew and hence, it is difficult to efficiently handle timing issues such as the setup and the hold time violations. In this work, we explore asynchronous design approach to address these challenges in subthreshold operation. We employ critical-path replica to generate completion signals of combinational logic blocks and use classical four-phase handshaking for communication between pipeline flip-flops. Since the proposed design approach uses only local clock buffers, it is easier to handle timing problems compared to synchronous designs. We compared iso-yield minimum energy dissipation of two design approaches (synchronous and asynchronous) in an inverter chain. Despite leakage overhead due to pad delay of critical-path delay line and ?return-to-zero? time of four-phase handshaking, the proposed asynchronous design shows 71% energy savings compared to its synchronous counterpart. To demonstrate subthreshold operation of the proposed design approach, we fabricated an 8-tap FIR filter in 90 nm CMOS. Measured oscilloscope plots of handshaking and output bus signals show that the design operates successfully below 300 mV. We also measured energy consumption of the FIR filter from 19 test chips-the average was 4.64 pJ and the standard deviation was 0.3526 pJ.

Journal ArticleDOI
TL;DR: In this article, a comprehensive physics-based surface potential and drain current model for the negative capacitance field effect transistor is presented, aimed to evaluate the potentiality of such transistors for low-power switching applications.
Abstract: In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this letter, a comprehensive physics-based surface potential and drain current model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. Moreover it provides a model core for memories devices relying on the hysteretic behavior of the ferroelectric gate insulator.

01 Jan 2010
TL;DR: The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate to enable the highest performance devices possible while maintaining extremely low power consumption.
Abstract: Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest perfor- mance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on- insulator devices, combined with a workfunction engineered mid-gap metal gate.

Journal ArticleDOI
TL;DR: A design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic applications and is largely applicable to designing other sound/graphic and streaming processors.
Abstract: We present a design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic applications. Our approach employs i) architecture-level parallelism to compensate throughput degradation, ii) a configurable V T balancer to mitigate the V T mismatch of nMOS and pMOS transistors operating in sub/near threshold, and iii) a fingered-structured parallel transistor that exploits V T mismatch to improve current drivability. Additionally, we describe the selection procedure of the standard cells and how they were modified for higher reliability in the subthreshold regime. All these concepts are demonstrated using SubJPEG, a 1.4 ×1.4 mm2 65 nm CMOS standard-V T multi-standard JPEG co-processor. Measurement results of the discrete cosine transform (DCT) and quantization processing engines, operating in the subthreshold regime, show an energy dissipation of only 0.75 pJ per cycle with a supply voltage of 0.4 V at 2.5 MHz. This leads to 8.3× energy reduction when compared to using a 1.2 V nominal supply. In the near-threshold regime the energy dissipation is 1.0 pJ per cycle with a 0.45 V supply voltage at 4.5 MHz. The system throughput can meet 15 fps 640 × 480 pixel VGA standard. Our methodology is largely applicable to designing other sound/graphic and streaming processors.

Journal ArticleDOI
22 Jan 2010
TL;DR: In this paper, a work function engineered mid-gap metal gate was used to reduce the switching energy of transistors for sub-threshold operation at 0.3 V and achieved a 97% reduction in switching energy compared to conventional transistors.
Abstract: Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the performance of vertical band-to-band tunneling FETs whose operation is based on the enhancement of the gate-induced drain leakage mechanism of MOSFETs.
Abstract: Using an atomistic full-band quantum transport solver, we investigate the performances of vertical band-to-band tunneling FETs (TFETs) whose operation is based on the enhancement of the gate-induced drain leakage mechanism of MOSFETs, and we compare them to lateral p-i-n devices. Although the vertical TFETs offer larger tunneling areas and therefore larger on currents than their lateral counterparts, they suffer from lateral source-to-drain tunneling leakage away from the gate contact. We propose a design improvement to reduce the off current of the vertical TFETs, maintain large on currents, and provide steep subthreshold slopes.

Journal ArticleDOI
TL;DR: In this article, the authors used an indium oxide (In2O3) thin film as the n-channel active layer by RF sputtering at room temperature and showed a thickness-dependent performance in the range of 48-8 nm, which is ascribed to the total carrier number in the active layer.
Abstract: Thin-film transistors (TFTs) were fabricated using an indium oxide (In2O3) thin film as the n-channel active layer by RF sputtering at room temperature. The TFTs showed a thickness-dependent performance in the range of 48-8 nm, which is ascribed to the total carrier number in the active layer. Optimum device performance at 8-nm-thick In2O3 TFTs had a field-effect mobility of 15.3 cm2 · V-1 · s-1, a threshold voltage of 3.1 V, an ON-OFF current ratio of 2.2 × 108, a subthreshold gate voltage swing of 0.25 V · decade-1, and, most importantly, a normally OFF characteristic. These results suggest that sputter-deposited In2O3 is a promising candidate for high-performance TFTs for transparent and flexible electronics.