Showing papers on "Subthreshold conduction published in 2011"

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference

Abstract: A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology. The reference voltage can be approximated by the difference of transistor threshold voltages at room temperature. Accurate subthreshold design allows the circuit to work at room temperature with supply voltages down to 0.45 V and an average current consumption of 5.8 nA. Measurements performed over a set of 40 samples showed an average temperature coefficient of 165 ppm/ C with a standard deviation of 100 ppm/ C, in a temperature range from 0 to 125°C. The mean line sensitivity is ≈0.44%/V, for supply voltages ranging from 0.45 to 1.8 V. The power supply rejection ratio measured at 30 Hz and simulated at 10 MHz is lower than -40 dB and -12 dB, respectively. The active area of the circuit is ≈0.043mm2.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Effects of excess oxygen on operation characteristics of amorphous In-Ga-Zn-O thin-film transistors

Abstract: Operation characteristics of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) were improved to a subthreshold voltage swing (S) of 217 mV (decade)−1, a mobility of ∼11.4 cm2 (Vs)−1, and a threshold voltage (Vth) of 0.1 V by O3 annealing at a temperature as low as 150 °C. However, the O3 annealing at 300 °C caused serious deterioration and exhibited a bistable transition between a large S state and a large Vth state. This transition is attributed to incorporation of excess oxygen and associated subgap defects with a negative-U characteristic. It also explains why a-IGZO channels deposited at high oxygen pressures do not produce operating TFTs.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Abstract: A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

Abstract: A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao-Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges.

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Abstract: SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

Abstract: SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.

Scaling Between Channel Mobility and Interface State Density in SiC MOSFETs

Abstract: The direct impact of the SiO2/4H-SiC interface state density (Dit) on the channel mobility of lateral field-effect transistors is studied by tailoring the trap distribution via nitridation of the thermal gate oxide. We observe that mobility scales like the inverse of the charged state density, which is consistent with Coulomb-scattering-limited transport at the interface. We also conclude that the Dit further impacts even the best devices by screening the gate potential, yielding small subthreshold swings and poor turn-ON characteristics.

A Sub-500 mV Highly Efficient Active Rectifier for Energy Harvesting Applications

Abstract: This paper presents a highly efficient, ultra-low-voltage active full wave rectifier. A two-stage concept is used including a first passive stage and only one active diode as second stage. A bulk-input comparator working in the subthreshold region is used to drive the switch of the active diode. The voltage drop over the rectifier is some tens of millivolt, which results in voltage and power efficiencies of over 90%. The design was successfully implemented in an 0.35 μm CMOS technology. The measured power consumption of the comparator is 266 nW@500 mV and the minimum operating voltage is 380 mV. Input voltages with frequencies up to 10 kHz can be rectified.

Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation

Abstract: The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in Cgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.

Heterojunction Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High on Current

Abstract: We propose a heterojunction vertical tunneling field-effect transistor and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high on current, thereby improving the scalability of TFETs for high performance. The turn-on in the pocket region of the device is dictated by the modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to the contribution of vertical tunneling in the pocket to the current. These factors can be engineered by tuning heterojunction band offsets.

Nanoparticle size dependent threshold voltage shifts in organic memory transistors

Abstract: The performance of organic field-effect transistor (OFET) memory devices with different size of gold nanoparticles (Au NPs) as charge trapping layers has been investigated We synthesized 15 nm, 20 nm and 25 nm of Au NPs through a citrate-reduction method and 3-aminopropyltriethoxysilane (APTES) functionalized substrates were used to form a monolayer of Au NPs In the programming/erasing operation, we observed reversible threshold voltage (Vth) shifts and reliable memory performances A strong size-dependent effect on Vth shifts and memory effect was observed Effect of size dependence on the mobilities (μ), on/off current ratios, subthreshold swings (S), data retention characteristics (>105 s) and endurance performances operation (>800 cycles) of memory devices are discussed The experimental results suggest a guideline for optimizing the size and density of Au NPs and their influence on the device properties

Competitive device performance of low-temperature and all-solution-processed metal-oxide thin-film transistors

Abstract: In this Letter, we described a solution-processed indium-gallium-zinc oxide thin-film transistors (TFTs) with a solution-processed aluminum oxide phosphate gate dielectric, fabricated at a maximum annealing temperature under 350 °C to be applicable to conventional fabrication process of flat-panel displays (FPDs). The solution-processed TFTs exhibited competitive device characteristics under 350 °C, including a field-effect mobility of 4.50 cm2/Vs, an on-to-off current ratio of ∼109, a threshold voltage of 2.34 V, and a subthreshold gate swing of 0.46 V/dec, making them applicable to the future backplane of FPDs.

Effects of band-tails on the subthreshold characteristics of nanowire band-to-band tunneling transistors

Abstract: High source doping is required to support the high electric fields necessary to provide sufficient drive currents in interband tunnel field effect transistors (TFETs). High doping is associated with band-tails in the density of states that decay exponentially into the bandgap with decay constants that can be comparable to the room temperature thermal energy kBT. This compromises the core operational principal of a TFET of a hard energy cut-off to the injected channel carrier distribution provided by the source valence band edge. If the band-tails are limited to the source region, they have minimal effect for short channels ≤10 nm, since the leakage current is dominated by direct, coherent tunneling through the channel. For longer 20 nm channels, source band-tails can double the inverse subthreshold slope but still leave it below the ideal 60 mV/decade value with on-off current ratios greater than 106 using a supply voltage of 0.4 V. Band-tails both in the source and channel are more detrimental for both 1...

An Area and Power-Efficient Analog Li-Ion Battery Charger Circuit

Abstract: The demand for greater battery life in low-power consumer electronics and implantable medical devices presents a need for improved energy efficiency in the management of small rechargeable cells. This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger with high energy efficiency. The charger presented here utilizes the tanh basis function of a subthreshold operational transconductance amplifier to smoothly transition between constant-current and constant-voltage charging regimes without the need for additional area- and power-consuming control circuitry. Current-domain circuitry for end-of-charge detection negates the need for precision-sense resistors in either the charging path or control loop. We show theoretically and experimentally that the low-frequency pole-zero nature of most battery impedances leads to inherent stability of the analog control loop. The circuit was fabricated in an AMI 0.5-μm complementary metal-oxide semiconductor process, and achieves 89.7% average power efficiency and an end voltage accuracy of 99.9% relative to the desired target 4.2 V, while consuming 0.16 mm2 of chip area. To date and to the best of our knowledge, this design represents the most area-efficient and most energy-efficient battery charger circuit reported in the literature.

Low-Temperature Solution Processing of AlInZnO/InZnO Dual-Channel Thin-Film Transistors

Abstract: In this letter, we proposed solution-processed AlInZnO (AIZO)/InZnO (IZO) dual-channel thin-film transistors to realize both proper switching behavior and competitive device performance at the low annealing temperature of 350°C. A thin IZO layer provides a higher carrier concentration, thereby maximizing the charge accumulation and yielding high saturation mobility μsat, whereas a thick AIZO layer controls the charge conductance resulting in suitable threshold voltage Vth. We therefore obtain excellent device characteristics at 350°C with μsat of 1.57 cm2/V ·s, Vth of 1.28 V, an on/off ratio of ~1.4 × 107, and a subthreshold gate swing of 0.59 V/dec.

Custom IC for Ultralow Power RF Energy Scavenging

Abstract: This letter presents a custom IC that provides an efficient interface between an ultralow power RF rectifying antenna (rectenna) power source and a microbattery for maximum power scavenging. The energy scavenger IC operates a boost converter in pulsed fixed-frequency discontinuous conduction mode to present a positive resistance to the rectenna. It uses current-starved circuitry, a nonoverlapping gate drive, and a subthreshold current source to achieve a nominal supply current in the 200-nA range for V DD = 2.5 V. Experimental results are given with the IC scavenging energy from a 1.93-GHz patch rectenna to a battery with voltages ranging from 2.5 to 4.15 V. Overall conversion efficiency including all control losses is demonstrated at over 35% at an input power of just 1.5 μW and at over 70% at input power levels over 30 μW. The IC is fabricated in a 5-V, 0.35-μm CMOS process. Although the IC was designed for RF energy scavenging, the low-power boost converter can be applied to other power sources such as wind, vibration, and temperature.

Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing

Abstract: We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

Abstract: While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance (such as on noise margin and delay) in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage.

A 250 mV, 352 $\mu$ W GPS Receiver RF Front-End in 130 nm CMOS

Abstract: A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of - 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

Improvement of carrier ballisticity in junctionless nanowire transistors

Abstract: In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballisticity in subthreshold and higher ballisticity above threshold compare to conventional inversion-mode transistors, according to quantum mechanical simulations. The lower degradation of the ballisticity above threshold region gives the JNT near-ballistic transport performance and hence a high current drive. On the other hand, lower ballisticity in subthreshold region helps reducing the off-current and improves the subthreshold slope. A three-dimensional quantum mechanical device simulator based on the nonequilibrium Green’s function formalism in the uncoupled mode-space approach has been developed to extract the physical parameters of the devices.

Electrical Performance Optimization of Nanoscale Double-Gate MOSFETs Using Multiobjective Genetic Algorithms

Abstract: In this paper, a new multiobjective genetic algorithm (MOGA)-based approach is proposed to optimize the electrical performance of double-gate (DG) MOSFETs for nanoscale CMOS digital applications. The proposed approach combines the universal optimization and fitting capability of MOGAs and the cost-effective optimization concept of quantum correction to achieve reliable and optimized designs of DG MOSFETs for nanoelectronics analog and digital circuit simulations. The dimensional and electrical parameters of the DG MOSFET (threshold voltage rolloff, off-current, drain-induced barrier lowering, subthreshold swing ( S), output conductance, and transconductance) have been ascertained, and a compact analytical expression, including quantum effects, has been presented. The developed compact models are used to formulate different objective functions, which are the prerequisite of the multiobjective optimization. The optimized design can also be incorporated into a circuit simulator to study and show the impact of our approach on a nanoscale CMOS-based circuit design.

Low voltage low power CMOS temperature sensor circuit

Abstract: The present invention provides an ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation particularly well suited for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is very important in passive RFID applications. The temperature sensor may be part of a passive RFID tag and incorporates a temperature sensor core, proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) delay generators, and a time-to-digital differential readout circuit. In one embodiment, the sensor is embedded inside a passive UHF RFID tag fabricated with a conventional 0.18 μm 1P6M CMOS process. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 33 samples/s and achieves an inaccuracy of +1/−0.8° C. from −10° C. to 30° C. after calibration.

Low-power temperature-to-frequency converter consisting of subthreshold CMOS circuits for integrated smart temperature sensors

Abstract: A low-power temperature-sensing oscillator was developed using a 0.35- μ m standard CMOS process. This oscillator generates a clock pulse whose frequency is proportional to absolute temperature (PTAT frequency). It consists of a PTAT current generator controlled with an external reference clock and a frequency-locked loop biased with an external reference voltage. The PTAT current generator makes use of the exponential current characteristic of MOSFETs operated in the subthreshold region. Theoretical analyses and experimental results showed that the circuit can be used as a temperature sensor with a low-power consumption of 10 μ W or less. The temperature coefficient of the output frequency was insensitive to variation in device parameters, so the sensor circuit can be used only with one-point calibration. Its temperature-sensing error was from − 1.8 to + 1 ° C in a temperature range of 10–80 ° C. This temperature sensor would be suitable for use in subthreshold-operated, power-aware LSIs.

High mobility top-gate and dual-gate polymer thin-film transistors based on diketopyrrolopyrrole-naphthalene copolymer

Abstract: In this letter, the performance characteristics of top-gate and dual-gate thin-film transistors (TFTs) with active semiconductor layers consisting of diketopyrrolopyrrole-naphthalene copolymer are described. Optimized top-gate TFTs possess mobilities of up to 1 cm 2 /V s with low contact resistance and reduced hysteresis in air. Dual-gate devices possess higher drive currents as well as improved subthreshold and above threshold characteristics compared to single-gate devices. We also describe the reasons that dual-gate devices result in improved performance. The good stability of this polymer combined with their promising electrical properties make this material a very promising semiconductor for printable electronics.

Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach

Abstract: This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal READ static noise margin (RSNM) because of the reduced READ disturb. For 4T cells, the nearly ideal values of Vwrite,0 and Vwriet,1 guarantee the positive nominal WRITE static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between WRITE time (for selected cells) and WRITE disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger μRSNM and a slightly worse σ-RSNM shows a comparable μ/σ ratio in RSNM with the 6T cell. Further more, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced σ-RSNM can outperform the 6T cell. For WRITE operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between WRITE time and WRITE disturb needs to be carefully examined to ensure an adequate margin considering device variability.

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage

Abstract: In this paper, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance change and transconductance-to-current ratio change methods, using analytical modeling and experimental data obtained on advanced UTB SOI MOSFETs. It is shown that, although these two methods have the same physical background, they feature radically different behaviors with respect to the drain voltage effect. In particular, the transconductance change method yields a threshold voltage value, which regularly increases with drain voltage, and interpretation, as well as analytical expression for this dependence, is provided. In contrast, for the transconductance-to-current ratio change method, the increase of the extracted threshold voltage value with drain voltage is smaller and rapidly saturates; hence, the threshold voltage extraction is more stable and reliable. Modeling derivations are found to be in excellent agreement with measurements on long-channel UTB SOI MOSFETs as well as 2-D simulations.

Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

Abstract: An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage models are compared with the Atlas simulation results, with variables being the device dimensions, the interface-charge region length and the interface-charge density. A good agreement between the model and simulation results has been observed by calibrating as a constant parameter the gate voltage included in the position of the minimum potential and the carrier charge-sheet density at the potential minimum that is adequate to achieve the turn-on condition.

Broken-Gap Tunnel MOSFET: A Constant-Slope Sub-60-mV/decade Transistor

Abstract: We propose a novel low-power transistor device, called the broken-gap tunnel MOSFET (BG-TMOS), which is capable of achieving constant sub-60-mV/decade inverse subthreshold slopes S at room temperature. Structurally, the device resembles an ungated broken-gap heterostructure Esaki region in series with a conventional MOSFET. The gate voltage independence of the energy spacing between the conduction and valence bands at the heterojunction is the key to producing a constant S <; 60 mV/decade, which can be tuned by properly engineering the material composition at this interface. In contrast to the tunneling field-effect transistor, the tunnel junction in the BG-TMOS is independent of the electrostatics in the channel region, enabling the use of 2-D architectures for improved current drive without degradation of S -attractive features from a circuit design perspective. Simulations show that the BG-TMOS can exceed MOSFET performance at low supply voltages.