Showing papers on "Subthreshold conduction published in 2012"

High-detectivity multilayer MoS(2) phototransistors with spectral response from ultraviolet to infrared.

Abstract: Phototransistors based on multilayer MoS(2) crystals are demonstrated with a wider spectral response and higher photoresponsivity than single-layer MoS(2) phototransistors. Multilayer MoS(2) phototransistors further exhibit high room temperature mobilities (>70 cm(2) V(-1) s(-1) ), near-ideal subthreshold swings (~70 mV decade(-1) ), low operating gate biases (<5 V), and negligible shifts in the threshold voltages during illumination.

Near-threshold voltage (NTV) design: opportunities and challenges

Abstract: Moore's Law will continue providing abundance of transistors for integration, only to be limited by the energy consumption. Near threshold voltage (NTV) operation has potential to improve energy efficiency by an order of magnitude. We discuss design techniques necessary for reliable operation over a wide range of supply voltage — from nominal down to subthreshold region. The system designed for NTV can dynamically select modes of operation, from high performance, to high energy efficiency, to the lowest power.

22-nm fully-depleted tri-gate CMOS transistors

Abstract: At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS The use of tri-gate transistors provides steep subthreshold slopes (∼70 mV/decade) and very low DIBL (∼50 mV/V) values that are critical for low voltage operation Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch This enables an SRAM cell size of 0092 μm2 High yield and reliability have been demonstrated on multiple microprocessors

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Abstract: This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold

Abstract: This paper surveys, reviews, and critiques analytic models of MOSFET short-channel effects (SCEs) in subthreshold published over the past four decades. In the first half of this paper, the published models on SCEs are categorized into the following four main groups based on their approach: 1) charging sharing models; 2) empirical expressions; 3) polynomial potential models; and 4) analytic solutions to 2-D Poisson's equation. The strength and weakness of each approach are elaborated in terms of its physical soundness and predictive ability. A key development was the exponential dependence of SCE on channel length (L) , SCE ~ exp(-L/l0), leading to the introduction of scale length (l0). In the second half of this paper, the predictions of each analytic SCE model are examined by generic 2-D numerical simulations. In particular, the merit of each model is judged by its prediction on the scale length (l0) as a function of the thickness and dielectric constant (κ) of the gate insulator. Only one model, i.e., the generalized scale length model that treated the silicon and insulator regions as two distinct dielectric regions with shared boundary conditions, correctly predicted the MOSFET scale length under all dielectric constant and thickness conditions. A variation of the generalized scale length model applies to recent multiple-gate MOSFETs near the limit of scaling.

Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs

Abstract: A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao-Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET.

A Compact Model of Quantum Electron Density at the Subthreshold Region for Double-Gate Junctionless Transistors

Abstract: A compact model of quantum electron density at the subthreshold region is derived for junctionless (JL) double-gate (DG) FETs. The proposed quantum model is obtained under two different quantum confinement conditions. One is for a case of a thick channel and a heavily doped channel, where quantum confinement effects (QCEs) are modeled by a 1-D quantum harmonic oscillator. The other is for a case of a thin channel, where QCEs are modeled by the use of a 1-D quantum well surrounded by high potential barriers and an energy correction term coming from the depletion charge. It is shown that, regardless of the channel thickness, the quantum confinement is higher in JL than in inversion-mode (IM) DG FETs. However, for a thin channel, the quantum threshold voltage shift is less severe in JL than in IM DG FETs. The proposed model gives an analytical expression for the threshold voltage shift due to QCEs, which can be used as a quantum correction term for compact modeling.

Fundamental limitations of conventional-FET biosensors: Quantum-mechanical-tunneling to the rescue

Abstract: Electrical detection of biomolecules using Field-Effect-Transistors (FETs) [1–5] is very attractive, since it is label-free, inexpensive, allows scalability and on-chip integration of both sensor and measurement systems. Nanostructured FETs, especially nanowires have gained special importance due to their high electrostatic control and large surface-to-volume ratio. In order to configure the FET as a biosensor (Fig. 1(a)), the dielectric/oxide layer on the semiconductor is functionalized with specific receptors. These receptors capture the desired target biomolecules (a process called conjugation), which due to their charge produce gating effect on the semiconductor, thus changing its electrical properties such as current, conductance etc. Thus it is intuitive, that greater the response of the FET to the gating effect, higher will be its sensitivity where sensitivity can be defined as the ratio of change in current due to biomolecule conjugation to the initial current (before conjugation). While the highest response to gating effect can be obtained in the subthreshold region, the conventional FETs (CFET) suffer severely due to the theoretical limitation on the minimum achievable Subthreshold Swing (SS) of [K B T/q ln(10)] due to the Boltzmann tyranny (Fig. 1(b)) effect where K B is the Boltzmann constant and T is the temperature. This also poses fundamental limitations on the sensitivity and response time of CFET based biosensors [6]. In recent times, Tunnel- FETs have attracted a lot of attention for low power digital applications [7]–[17], due to their ability to overcome the fundamental limitation in SS (60 mV/decade) of CFETs. Recently, it has been shown that the superior subthreshold behavior of TFETs can be leveraged to achieve highly efficient biosensors [6]. This is possible, thanks to the fundamentally different current injection mechanism in TFETs in the form of band-to-band tunneling [17]. The working principle of TFET biosensors is illustrated in Fig. 1c.

An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC

Abstract: This paper presents an output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current efficiency. The pass transistor is designed to work in the linear region at heavy load to save silicon area, and a symmetrically matched current-voltage mirror is used to implement the AB scheme with accurate current sensing for the full load range. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily but exponentially increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Undershoot voltage is hence dramatically reduced. Stability of the ABSTUR LDR is thoroughly analyzed and tradeoffs between the undershoot-reduction strength and the light load stability are discussed. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

A −32dBm sensitivity RF power harvester in 130nm CMOS

Abstract: This paper discusses a RF power harvester optimized for sensitivity and therefore wireless range, for applications requiring intermittent communication. The RF power harvester produces a 1V output at −32dBm sensitivity and 915MHz. This is achieved using a CMOS rectifier operating in the subthreshold region and an off-chip impedance matching network for boosting the received voltage. Equations predicting the rectifier performance are presented and verified through measurements of multiple rectifiers using different transistors in a 130nm CMOS process.

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS

Abstract: This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit. The proposed methods accomplish this by minimizing the circuit's ratio of leakage to active current. The first method, super pipelining, increases the number of pipeline stages compared to conventional ultra low voltage (ULV) pipelining strategies, reducing the leakage/dynamic energy ratio and simultaneously improving performance and energy efficiency. Measurements of super-pipelined multipliers demonstrate 30% energy savings and 1.6× performance improvement. Since super pipelining reduces the logic depth between registers, two-phase latch based design is employed to compensate for reduced averaging effects and provide better variation tolerance. The second technique introduces a parallel-pipelined architecture that suppresses leakage energy by ensuring full utilization of functional units and reduces memory size. We apply these techniques to a 16-b 1024-pt complex-valued Fast Fourier Transform (FFT) core along with low-power first-in first-out (FIFO) design and robust clock distribution network. The FFT core is fabricated in 65 nm CMOS and consumes 15.8 nJ/FFT with a clock frequency of 30 MHz and throughput of 240 Msamples/s at Vdd=270 mV, providing 2.4× better energy efficiency than current state-of-art and >; 10× higher throughput than typical ULV designs. Measurements of 60 dies show modest frequency (energy) σ/μ spreads of 7% (2%).

Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

Abstract: In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-W active power consumption.

A Nonpiecewise Model for Long-Channel Junctionless Cylindrical Nanowire FETs

Abstract: A nonpiecewise drain current model is formulated for long-channel junctionless (JL) cylindrical nanowire (CN) FETs It is obtained by using the Pao-Sah integral and a continuous charge model, which is derived by extending the parabolic potential approximation in all regions of the device operation The proposed nonpiecewise model analytically describes the bulk and surface current mechanisms in JL CN FETs from the subthreshold region through the linear region to the saturation region without any fitting parameters In addition, for each of these operation regions, the model reduces to simple expressions that explain the working principle of JL CN FETs The model is compared with numerical simulations and shows good agreement

A 0.09 $\mu$ W Low Power Front-End Biopotential Amplifier for Biosignal Recording

Abstract: This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm2. With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 μW , respectively.

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

Abstract: This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

Demonstration of scaled Ge p-channel FinFETs integrated on Si

Abstract: We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1] Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 05V), good SCE control and high transconductance (12 mS/μm at 1V, 105 mS/μm at 05V) are achieved The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date

Role of self-assembled monolayer passivation in electrical transport properties and flicker noise of nanowire transistors.

Abstract: Semiconductor nanowires have achieved great attention for integration in next-generation electronics. However, for nanowires with diameters comparabletotheDebyelength,whichwouldgenerally berequiredforone-dimensionaloperation,surfacestatesdegradethedeviceperformanceand increase the low-frequency noise. In this study, single In2O3 nanowire transistors were fabricated and characterized before and after surface passivation with a self-assembled monolayer of1-octadecanethiol(ODT).Electrical characterization ofthetransistorsshowsthat device performance can be enhanced upon ODT passivation, exhibiting steep subthreshold slope (∼64 mV/dec), near zero threshold voltage (∼0.6 V), high mobility (∼624 cm 2 /V 3 s), and high on-currents (∼40 μA). X-ray photoelectron spectroscopy studies of the ODT- passivated nanowires indicate that the molecules are bound to In2O3 nanowires through the thiol linkages. Device simulations using a rectangular geometry to represent the nanowire indicate that the improvement in subthreshold slope and positive shift in threshold voltage can be explained in terms of reduced interface trap density and changes in fixed charge density. Flicker (low-frequency, 1/f) noise measurements show that the noise amplitude is reduced following passivation. The interface trap density before and after ODT passivation is profiled throughout the band gap energy using the subthreshold currentvoltage character- istics and is compared to the values extracted from the low-frequency noise measurements. The results indicate that self-assembled monolayer passivation is a promising optimization technologyfortherealizationoflow-power,low-noise,andfast-switchingapplicationssuchas logic, memory, and display circuitry.

A Low-Voltage, Low-Power, and Low-Noise UWB Mixer Using Bulk-Injection and Switched Biasing Techniques

Abstract: This paper presents a low-voltage, low-power, low-noise, and ultra-wideband (UWB) mixer using bulk-injection and switched biasing techniques. The bulk-injection technique is implemented for a low supply voltage, thus resulting in low power consumption. This technique also allows for a flat conversion gain over a wide range of frequencies covering the full UWB band; this is a result of the integration of the RF transconductance stage and the local oscillator switching stage into a single transistor that is able to eliminate parasitic effects. Moreover, since the bulk-injection transistors of the mixer are designed to operate in the subthreshold region, current dissipation is reduced. A switched biasing technique for the tail current source, in place of static biasing, is adopted to reduce noise. The effects of modulated input signals, such as AM and FM, are simulated and measured to demonstrate the robustness of the switched biasing technique. The proposed mixer offers a measured conversion gain from 7.6 to 9.9 dB, a noise figure from 11.7 to 13.9 dB, and input third-order intercept point from - 10 to - 15.5 dBm, over 2.4 to 11.9 GHz, while consuming only 0.88 mW from a 0.8-V supply voltage. The chip size including the test pads is 0.62×0.58 mm2 using a 0.18-μm RF CMOS process.

A CMOS Voltage Reference Based on Mutual Compensation of Vtn and Vtp

Abstract: A novel temperature-stable nonbandgap voltage reference, which is compatible with standard CMOS technology, is presented in this brief. No diodes or parasitic bipolar transistors are used. Based on mutual temperature compensation of the threshold voltages of nMOS and pMOS transistors, a temperature-insensitive voltage reference with significant reduction in temperature dependence of mobility is achieved without using subthreshold characteristics. The problem of a fixed voltage reference value is also avoided by different parameter design. Experimental results of the proposed voltage reference implemented with a 0.35-μm CMOS process demonstrate that the output of the voltage reference is 847.5 mV, a temperature coefficient of 11.8 ppm/°C with a temperature range from 0 °C to 130 °C is obtained at 3-V power supply, a power-supply noise attenuation of 72 dB is achieved without any filtering capacitor, and the line regulation is better than 0.185 mV/V from 1.8-V to 4.5-V supply voltage dissipating a maximum supply current of 8 μA. The active area of the presented voltage reference is 90 μm ×120 μm.

Self-Aligned Indium–Gallium–Zinc Oxide Thin-Film Transistor With Phosphorus-Doped Source/Drain Regions

Abstract: Self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with phosphorusdoped source/drain regions are developed in this letter. The resulting a-IGZO TFT exhibits high thermal stability and good electrical performance, including field-effect mobility of 5 cm2/V · s, a threshold voltage of 5.6 V, a subthreshold swing of 0.5 V/dec, and an on/off current ratio of 6 × 107. With scaling down of the channel length, good characteristics are also obtained with a small shift in the threshold voltage and no degradation in the subthreshold swing.

Analytical Delay Model Considering Variability Effects in Subthreshold Domain

Abstract: The demand of ultralow-power circuits has significantly increased in the last few years. Owing to its great potential in energy savings, the use of supply voltage near or below the transistors' threshold voltages has gained particular attention. Designing these kinds of circuits is still a challenge, particularly when latest advanced process technologies are employed. This brief proposes novel analytical delay models for CMOS circuits running in the subthreshold regime. The delay models proposed here take the effects of the process variability and of the transient variation of the transistors' on-current during the switching into account. Owing to this, delays are predicted with accuracy significantly higher than existing accurate delay models. Furthermore, the novel models are also suitable for gates with transistors' stacks.

Flexure-FET biosensor to break the fundamental sensitivity limits of nanobiosensors using nonlinear electromechanical coupling

Abstract: In this article, we propose a Flexure-FET (flexure sensitive field effect transistor) ultrasensitive biosensor that utilizes the nonlinear electromechanical coupling to overcome the fundamental sensitivity limits of classical electrical or mechanical nanoscale biosensors. The stiffness of the suspended gate of Flexure-FET changes with the capture of the target biomolecules, and the corresponding change in the gate shape or deflection is reflected in the drain current of FET. The Flexure-FET is configured to operate such that the gate is biased near pull-in instability, and the FET-channel is biased in the subthreshold regime. In this coupled nonlinear operating mode, the sensitivity (S) of Flexure-FET with respect to the captured molecule density (Ns) is shown to be exponentially higher than that of any other electrical or mechanical biosensor. In other words, while , classical electrical or mechanical biosensors are limited to Sclassical ∼ γ3NS or γ4 ln(NS), where γi are sensor-specific constants. In addition, the proposed sensor can detect both charged and charge-neutral biomolecules, without requiring a reference electrode or any sophisticated instrumentation, making it a potential candidate for various low-cost, point-of-care applications.

Bipolar effects in unipolar junctionless transistors

Abstract: In this work, we analyze hysteresis and bipolar effects in unipolar junctionless transistors. A change in subthreshold drain current by 5 orders of magnitude is demonstrated at a drain voltage of 2.25 V in silicon junctionless transistor. Contrary to the conventional theory, increasing gate oxide thickness results in (i) a reduction of subthreshold slope (S-slope) and (ii) an increase in drain current, due to bipolar effects. The high sensitivity to film thickness in junctionless devices will be most crucial factor in achieving steep transition from ON to OFF state.

Standard cell sizing for subthreshold operation

Abstract: Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.

SLC: Split-control Level Converter for dense and stable wide-range voltage conversion

Abstract: Ultra-low voltage design makes signal level conversion a critical component in modern low power designs. This paper proposes a static level converter operating in the subthreshold regime, called SLC (Split-control Level Converter). Using a novel circuit structure, SLC effectively eliminates the high leakage and short circuit currents in previous approaches. Designed for 300mV to 2.5V conversion and fabricated in 130nm CMOS, measured results show 2.3×, 9.9×, and 5.9× improvements over conventional DCVS structures in delay, static power, and energy per transition, respectively. Even with the smallest area among wide-range level converters, it also has 5.2× smaller standard deviation in delay and only 5.6% change in FO4 delay with 10% V DDL drop, demonstrating robustness.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

Abstract: This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( $S.S.$ ) and comparable trap-induced $V_{T}$ shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage $(V_{\rm dd})$ , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause $\sim$ 24%–27% and $\sim$ 13%–15% variations in leakage and delay at $V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$ , respectively, for the logic circuits evaluated.

Suppress temperature instability of InGaZnO thin film transistors by N2O plasma treatment, including thermal-induced hole trapping phenomenon under gate bias stress

Abstract: An abnormal subthreshold leakage current is observed at high temperature, which causes a notable stretch-out phenomenon in amorphous InGaZnO thin film transistors (a-IGZO TFTs). This is due to trap-induced thermal-generated holes accumulating at the source region, which leads to barrier lowering on the source side and causes an apparent subthreshold leakage current. In order to obtain superior thermal stability performance of a-IGZO TFTs, conducting N2O plasma treatment on active layer was expected to avert defects generation during SiO2 deposition process. Reducing defects generation not only suppresses subthreshold current stretch-out phenomenon but also significantly improves the bias stress stability in a-IGZO TFTs at high temperature.

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V T memory in 65nm CMOS

Abstract: Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-V T ) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-V T storage arrays and fill the gap of missing sub-V T memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.