Showing papers on "Subthreshold conduction published in 2013"

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Abstract: In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along the channel, while assuming a parabolic potential across the silicon thickness, which in turn leads to some explicit relationships of the subthreshold current, subthreshold slope (SS) and drain induced barrier lowering (DIBL). This approach has been assessed with Technology Computer Aided Design (TCAD) simulations, confirming that this represents an interesting solution for further implementation in generic JL DG MOSFETs compact models.

Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing

Abstract: To reduce the power consumption and improve the device performance in scaled CMOS integrated circuits, transistors with steep subthreshold swing (SS) is highly desirable. The tunnel field-effect transistor (TFET) based on the band-to-band tunneling has been suggested as a replacement to conventional MOSFETs. In order to improve the device performance of TFET, enhanced carrier transport across the tunneling junction is crucial. In this paper, source-pocket Si TFET is presented and successfully fabricated by laser annealing. This TFET has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance. The experimental data of the proposed paper, for the first time, shows steep SS (46 mV/dec at 1 pA/μm), excellent ION/IOFF ratio ( <; 107), and improved output characteristics at T = 300 K due to the dramatic reduction of the tunneling resistance. Compared with other TFET works, the proposed method is efficient to improve the device performance on TFET.

Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

Abstract: A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

Abstract: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier

Abstract: This work studies the potentials and challenges of designing ultra low-power analog circuits exploiting unique characteristics of Tunnel-FET (TFET). TFET can achieve ultra-low quiescent current (~pA). In the subthreshold operation, TFET exhibit subthreshold swing lower than 60mV/decade, and hence higher transconductance per bias current than the MOSFET. TFET also exhibit very weak temperature dependence, and higher output resistance. Among several challenges, TFET demonstrate higher Shot noise at low biasing current. Through design of TFET based Operational Transconductance Amplifier (OTA) these challenges and opportunities are discussed. For implantable bio-medical applications, TFET OTA based neural amplifier design is studied.

A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors

Abstract: Here, we propose an advanced compact analytical current-voltage model for organic field-effect transistors (OFETs), which can be incorporated into SPICE-type circuit simulators. We improved the output saturation behavior by introducing a new asymptotic function that also enables more precise low-voltage current and conductance fitting. A new expression for the subthreshold current was suggested to cover all operation regimes of OFETs. All model parameters were extracted by a systematic method, and the comparison of the modeled current with the experimental data on pentacene-based OFETs confirmed the validity of the model over a wide operation range.

Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

Abstract: With the exact solution of the 2-D Poisson's equation in cylindrical coordinates, analytical subthreshold behavior models for junctionless cylindrical surrounding-gate (JLCSG) MOSFETs are developed. Using these analytical models, subthreshold characteristics of JLCSG MOSFETs are investigated in terms of channel electrostatic potential distribution, subthreshold current, and subthreshold slope (SS). It is shown that the electrostatic potential distribution, subthreshold current, and SS predicted by the analytical models are in close agreement with 3-D numerical simulation results without the need of any fitting parameters. These analytical models not only provide useful physical insight into the subthreshold behaviors, but also offer basic design guideline for the nanoscale JLCSG MOSFETs.

Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs

Abstract: This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green's function formalism, employing an 8 × 8 k·p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics.

A 0.8-V 230- $\mu$ W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications

Abstract: This paper presents a ΣΔ modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm 2. The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230-μW power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.

Novel strong PUF based on nonlinearity of MOSFET subthreshold operation

Abstract: Many strong silicon physical unclonable functions (PUFs) are known to be vulnerable to machine-learning attacks due to linear separability of the output function. This significantly limits their potential as reliable security primitives. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation which injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a pair of two-dimensional n × k transistor arrays with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.2%. The average intra-class Hamming distance, a measure of response stability, is 4.17%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using machine-learning techniques of support-vector machine with radial basis function kernel and logistic regression for best nonlinear learnability, we observe that “information leakage” (rate of error reduction with learning) is much lower than for delay-based PUFs. Over a wide range of the number of observed challenge-response pairs, the error rate is 3-35X higher than for the delay-based PUF. We also demonstrate an enhanced SCAPUF design utilizing XOR scrambling and show that it has an up to 30X higher error rate compared to the XOR delay-based PUF.

Course and risk factors of functional impairment in subthreshold depression and anxiety

Abstract: Background Although persons with subthreshold depression or anxiety are known to be at risk for full-syndromal disorders, little is known about their functioning over time. In this study, we investigate the functional impairment of persons with subthreshold depression or anxiety over time, compared to that of controls. Furthermore, we evaluate which illness, personal, and environmental risk factors influence its course. Methods Data come from the Netherlands Study of Depression and Anxiety (N = 1,266, aged 1865). Linear mixed models were used to identify predictors of functional impairment at baseline, 1-, and 2-year follow-up. Risk factors were evaluated in their overall effect on functioning and on change in functioning over time, and whether they differed for respondents with and without subthreshold depression or anxiety. Results Functional impairment in subthreshold respondents improved over time, but remained much higher than in controls. Prior anxiety disorder, high neuroticism, low conscientiousness, more somatic conditions, and more childhood trauma all predicted greater functional impairment. Older age predicted lower functioning only in subthreshold respondents, while the effect of neuroticism was stronger in subthreshold respondents relative to controls. Conclusions Functional impairment in subthreshold respondents improved over time, but remained elevated compared to that of controls. Given continuously elevated levels of impairment, preventive interventions should be focused on persons with subthreshold symptoms; in particular those with prior anxiety disorder, high neuroticism, low conscientiousness, somatic conditions, or childhood trauma.

High Drain Current Density E-Mode ${\rm Al}_{2}{\rm O}_{3}$ /AlGaN/GaN MOS-HEMT on Si With Enhanced Power Device Figure-of-Merit $(4\times 10^{8}~{\rm V}^{2}\Omega^{-1}{\rm cm}^{-2})$

Abstract: In this paper, we report on the enhancement-mode (E-mode) Al2O3/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) on Si. The E-mode operation is due to the negative charges in the atomic layer deposited Al2O3 layer. The unrecessed E-mode MOS-HEMTs exhibit high drain current density with a low specific ON-state resistance (RON,sp) of 0.7 mΩ·cm2. A low gate leakage current showed enhancements in the subthreshold characteristics such as ION/IOFF ratio ~108 and subthreshold slope of 75 mV/decade. This E-mode device showed good retention characteristics of threshold voltage upto 105 s. Furthermore, the E-mode MOS-HEMT exhibits an OFF-state breakdown voltage of 532 V for short gate-to-drain distance (Lgd=4 μm) that records a high power device figure of merit (FOM=BV2/RON,sp) value of 4×108 V2Ω-1cm-2.

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

Abstract: This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region

Abstract: This report focuses on the development of an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs), which is valid in the subthreshold regime. From that we derive an expression for calculating the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain regions. The device is turned on by creating a conducting channel in the center of the silicon film, and turned off by depleting it. To achieve good I on / I off ratios, and to ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. The analytical model is compared with numerical simulation results from TCAD Sentaurus. Its validity is confirmed for long-channel, as well as for ultra-scaled devices having a channel length about 22 nm. Since the junctionless device is still in its infancy, an analytical model, especially for short-channel devices, can provide help to understand its electrostatic characteristics.

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

Abstract: The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

High-Temperature Operation of Diamond Junction Field-Effect Transistors With Lateral p-n Junctions

Abstract: High-temperature performance of diamond junction field-effect transistors (JFETs) with lateral p-n junctions is demonstrated. Diamond JFETs fabricated by n-type selective growth can be operated at 723 K, and show very low leakage currents of ~ 10-13 A and high ON/OFF ratios . Specific on-resistance decreases from 52.2 mΩ·cm2 at 300 K to 1.4 mΩ·cm2 at 723 K. At high temperatures, the device shows steep subthreshold swings very close to the theoretical limit. The low leakage currents are maintained even at a high drain voltage of -100 V. These excellent properties at high temperatures and high voltage show that diamond JFETs can work in harsh environments.

An Analytical Threshold Voltage Model for Triple-Material Cylindrical Gate-All-Around (TM-CGAA) MOSFETs

Abstract: In this paper, an analytical threshold voltage model is proposed for a triple-material cylindrical gate-all-around MOSFET considering parabolic approximation of the potential along the radial axis. The center (axial) and the surface potential models are obtained by solving the 2-D Poisson's equation in the cylindrical coordinate system. This paper refutes the estimation of the natural length using surface potential as in previous work and proposes the use of center-potential-based natural length formulation for an accurate subthreshold analysis. The developed center potential model is used further to formulate the threshold voltage model and also extract drain-induced barrier lowering (DIBL) from the same. The effects of the device parameters like the cylinder diameter, oxide thickness, gate length ratio, etc., on the threshold voltage and DIBL are also studied in this paper. The model is verified by the simulations obtained from 3D numerical device simulator Sentaurus from Synopsys.

Subthreshold Dual Mode Logic

Abstract: In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept.

Low-distortion super-GOhm subthreshold-MOS resistors for CMOS neural amplifiers

Abstract: A low-distortion super-GOhm subthreshold MOS resistor is designed, fabricated and experimentally validated. The circuit is utilized as a feedback element in the body of a two-stage neural recording amplifier. Linearity is experimentally validated for 0.5 Hz to 5 kHz input frequency and over 0.3 to 0.9 V output voltage dynamic range. The implemented pseudo resistor is also tunable, making the high-pass filter pole adjustable. The circuit is fabricated in 0.13-μm CMOS process and consumes 96 nW from a 1.2 V supply to realize an over 500 GΩ resistance.

An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation

Abstract: A subthreshold ECG processor in 45-nm IBM SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (Emin) at the MEOP. SEC is shown to reduce Emin by 28% compared with the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% precorrection error rate pe. These results represent an improvement of 19× in beat-detection performance and 600× in pe over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state of the art while tolerating 16× more voltage variations.

A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure

Abstract: We proposed models of subthreshold characteristics for deep nanoscale short channel asymmetric junctionless Double-Gate (DG) MOSFETs. Models were derived by solving 2-D Poisson’s equation using variable separation technique. The subthreshold behavior with structure asymmetry such as different gate oxide thicknesses and different gate biases between the front-gate and back-gate can be exactly described. Design parameters such as body doping, body thickness and channel length were considered. The models were verified by comparing with device simulations’ results.

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Abstract: Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.

A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

Abstract: A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.

Precise analytical model for short channel Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET

Abstract: A compact analytical model is presented for device electrostatics of nanoscale Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET, using isomorphic polynomial function for potential distribution. The model is based on solutions of 3D Laplace and Poisson’s equations for subthreshold and strong inversion region respectively. In this paper, the short-channel effects are precisely accounted for by introducing z dependent characteristic length and the developed electrostatics is tested against analysis of crossover point for device under test. Further, the modeled subthreshold slope for lightly doped CylG GAA MOSFET has been improved by introducing z dependent characteristic length and the position of minimum center potential in the channel is obtained by virtual cathode position. A new model is proposed for threshold voltage, based on shifting of inversion charge from center line to silicon insulator interface.

Performance limits for field effect transistors as terahertz detectors

Abstract: We present estimates of the performance limits of terahertz detectors based on the field effect transistors (FETs) operating in the regime of broadband detection. The maximal responsivity is predicted for short-channel FETs in the subthreshold regime. The conversion efficiency of the device, Q (defined as the ratio of the power dissipated by radiation-induced dc current to the THz dissipated power) has an absolute maximum as a function of two variables: the power and the frequency of the incoming radiation. The maximal value of Q is on the order of 10%.

Investigation of the RTN Distribution of Nanoscale MOS Devices From Subthreshold to On-State

Abstract: This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

Abstract: This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

Performance Limits for Field Effect Transistors as Terahertz Detectors

Abstract: We present estimates of the performance limits of terahertz detectors based on the field effect transistors (FET) in the regime of broadband detection. The maximal responsivity is predicted for short-channel FETs in the subthreshold regime. We also calculate the conversion efficiency Q of the device defined as the ratio of the power dissipated by radiation-induced dc current to the THz dissipated power. We show that Q has an absolute maximum as a function of two variables: the power and the frequency of the incoming radiation. The maximal value of Q is on the order of 10%