Showing papers on "Subthreshold conduction published in 2014"

23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement

Abstract: Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested from the surrounding environment is limited, the available output voltage of a harvester is low. Therefore, the design of a low-input-voltage (low-VIN) up-converter is critical to self-powered systems [1-3]. Moreover, the form factor is very constrained in applications such as wearable electronic devices and sensor networks. Recently, low-VIN charge pumps (CPs) for energy harvesting has been compared with DC-DC converters using a large inductor [1-3]. CPs introduced in [1] and [2] use the advanced process technology to push VIN down to the subthreshold region. The CP in [1] introduces a forward-body-biasing (FBB) technique, which improves the voltage conversion efficiency (VCE) for low VIN but shows poor power conversion efficiency (PCE). The CP in [2] achieves the lowest operation voltage. However, the design with a 10-stage CP provides low output power. This paper presents a CP with switching-body-biasing (SBB), adaptive-dead-time (AD), and switch-conductance (SW-G) enhancement techniques to improve the PCE for low VIN as well as to extend the maximum load current.

A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect

Abstract: This paper presents an analytical current-voltage model specifically formulated for 2-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor based field-effect transistors (FETs). The model is derived from the fundamentals considering the physics of 2D TMD crystals, and covers all regions of the FET operation (linear, saturation, and subthreshold) under a continuous function. Moreover, three issues of great importance in the emerging 2D FET arena: interface traps, mobility degradation, and inefficient doping have been carefully considered. The compact models are verified against 2-D device simulations as well as experimental results for state-of-the-art top-gated monolayer TMD FETs, and can be easily employed for efficient exploration of circuits based on 2D FETs as well as for evaluation and optimization of 2D TMD-channel FET design and performance.

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Abstract: This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV ( ~ 100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25 ° C.

A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer

Abstract: Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications.

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Abstract: Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

Abstract: In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

Abstract: This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

High-Speed Dual-Gate a-IGZO TFT-Based Circuits With Top-Gate Offset Structure

Abstract: Owing to bulk-accumulation, dual-gate (DG) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with top- and bottom-gates electrically tied together (DG-driving) exhibit 2.53 times higher ON-current and subthreshold voltage swing of ~ 180 mV/decade, which is 50% lower than that of single-gate (SG)-driven a-IGZO TFTs. Here, through simulation and experimental results, we demonstrate that the use of DG-driven back-channel-etched a-IGZO TFTs with a top-gate offset structure enhances the switching speed of a-IGZO TFT-based circuits. In particular, fabricated SG-driven and DG-driven 11-stage ring oscillators exhibited respective oscillating frequencies of 334 and 781 kHz.

Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier

Abstract: This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A well-defined procedure for the systematic design of subthreshold operational amplifiers op-amps is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-µm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70dB and a gain-bandwidth product of 18kHz, dissipating just 75nW. The active area of the chip is i¾?0.057mm2. Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.

Subthreshold attention deficit hyperactivity in children and adolescents: a systematic review.

Abstract: Subthreshold disorders, conditions with relevant psychiatric symptoms which do not meet the full criteria of a disorder according to the prevailing classification systems, have received increased attention recently. The current paper aims to present a systematic review of subthreshold attention-deficit/hyperactivity disorder (ADHD) in children and adolescents. Searching five computerised databases (Ovid MEDLINE, Psychinfo, PubMed, Scopus, Web of Science) with two categories of search terms [(1) subclinical; subsyndromal; subthreshold (2) ADHD] the authors examined the prevalence of subthreshold ADHD among children and adolescents, the comorbidity of subthreshold ADHD and whether there was already any impact of subthreshold ADHD on functioning. Before these questions were answered, the included articles were examined to see what kinds of definitions of child and adolescent subthreshold ADHD are used and what kinds of assessments are used for measuring subthreshold ADHD among children and adolescents. The results of the 18 articles included show that different definitions of subthreshold ADHD in children and adolescents exist, a large variety of instruments are used, the prevalence rate of subthreshold ADHD is wide-ranging (0.8–23.1 %), the comorbidity of subthreshold ADHD is high and there are several areas where subthreshold ADHD has a meaningful impact on functioning. All these suggest that focusing on subthreshold ADHD can be important in preventative interventions. The results of this systematic review support the dimensional approach of ADHD. Further research on uniform criteria of subthreshold ADHD is needed to support the inclusion of this condition in classification systems.

Analytical Models for Electric Potential, Threshold Voltage, and Subthreshold Swing of Junctionless Surrounding-Gate Transistors

Abstract: Analytical models for electric potential, threshold voltage, and subthreshold swing of the junctionless surrounding-gate field-effect transistors are presented. Poisson equation is solved and the electric potential is obtained. With the potential model, explicit expressions for threshold voltage and subthreshold swing are obtained. The analytical results are compared with those from simulations and excellent agreements are observed. The analytical models are useful not only for fast circuit simulations, but also for device design and optimization.

Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design

Abstract: This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.

CMOS Startup Charge Pump With Body Bias and Backward Control for Energy Harvesting Step-Up Converters

Abstract: A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 $\mu$ m CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds.

A Subthreshold Symmetric SRAM Cell With High Read Stability

Abstract: This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition, the read and write noise margins of the conventional six-transistor (6T) cell are 18 and 27 mV, respectively. The cell area is 1.57× the conventional 6T SRAM cell area in 45-nm design rules.

A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs

Abstract: This paper proposes a MOSFET-only, 20pA, 780ppm/°C current reference that consumes 23pW. The ultra-low power circuit exploits subthreshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows low supply voltage sensitivity of 0.58%/V and a load sensitivity of 0.25%/V.

Frequency Preference Response to Oscillatory Inputs in Two-dimensional Neural Models: A Geometric Approach to Subthreshold Amplitude and Phase Resonance.

Abstract: We investigate the dynamic mechanisms of generation of subthreshold and phase resonance in two-dimensional linear and linearized biophysical (conductance-based) models, and we extend our analysis to account for the effect of simple, but not necessarily weak, types of nonlinearities. Subthreshold resonance refers to the ability of neurons to exhibit a peak in their voltage amplitude response to oscillatory input currents at a preferred non-zero (resonant) frequency. Phase-resonance refers to the ability of neurons to exhibit a zero-phase (or zero-phase-shift) response to oscillatory input currents at a non-zero (phase-resonant) frequency. We adapt the classical phase-plane analysis approach to account for the dynamic effects of oscillatory inputs and develop a tool, the envelope-plane diagrams, that captures the role that conductances and time scales play in amplifying the voltage response at the resonant frequency band as compared to smaller and larger frequencies. We use envelope-plane diagrams in our analysis. We explain why the resonance phenomena do not necessarily arise from the presence of imaginary eigenvalues at rest, but rather they emerge from the interplay of the intrinsic and input time scales. We further explain why an increase in the time-scale separation causes an amplification of the voltage response in addition to shifting the resonant and phase-resonant frequencies. This is of fundamental importance for neural models since neurons typically exhibit a strong separation of time scales. We extend this approach to explain the effects of nonlinearities on both resonance and phase-resonance. We demonstrate that nonlinearities in the voltage equation cause amplifications of the voltage response and shifts in the resonant and phase-resonant frequencies that are not predicted by the corresponding linearized model. The differences between the nonlinear response and the linear prediction increase with increasing levels of the time scale separation between the voltage and the gating variable, and they almost disappear when both equations evolve at comparable rates. In contrast, voltage responses are almost insensitive to nonlinearities located in the gating variable equation. The method we develop provides a framework for the investigation of the preferred frequency responses in three-dimensional and nonlinear neuronal models as well as simple models of coupled neurons.

Oscillations emerging from noise-driven steady state in networks with electrical synapses and subthreshold resonance

Abstract: Oscillations play a critical role in cognitive phenomena and have been observed in many brain regions. Experimental evidence indicates that classes of neurons exhibit properties that could promote oscillations, such as subthreshold resonance and electrical gap junctions. Typically, these two properties are studied separately but it is not clear which is the dominant determinant of global network rhythms. Our aim is to provide an analytical understanding of how these two effects destabilize the fluctuation-driven state, in which neurons fire irregularly, and lead to an emergence of global synchronous oscillations. Here we show how the oscillation frequency is shaped by single neuron resonance, electrical and chemical synapses.The presence of both gap junctions and subthreshold resonance are necessary for the emergence of oscillations. Our results are in agreement with several experimental observations such as network responses to oscillatory inputs and offer a much-needed conceptual link connecting a collection of disparate effects observed in networks.

Electrical Noise in Heterojunction Interband Tunnel FETs

Abstract: We present an analysis of electrical noise in III-V heterojunction TFET (HTFET) Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction HTFET exhibits 40% less relative RTN amplitude at 03 V at gate lengths around 20 nm, over subthreshold Si-FinFET RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET In the range 10 GHz or more with operating voltages exceeding 03 V, HTFET input noise is worse due to the dominance of shot noise A differential amplifier with active load is used to examine the electrical noise performance at circuit level We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

Abstract: This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm 2 and it consumed 5.35 μW at V DD = 250 mV and f CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.

The Quantum Metal Ferroelectric Field-Effect Transistor

Abstract: It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous.

Low temperature characterization of 14nm FDSOI CMOS devices

Abstract: A detailed characterization of low temperature operation of n and p MOS devices from 14nm FDSOI CMOS technology has been conducted. The transfer characteristics measured between 77K and 300K exhibit very good performance for effective gate lengths down 15nm, emphasizing the very good control of short channel effects and subthreshold behavior. Moreover, the temperature dependence of the low field mobility clearly indicates that, for long devices, it is limited by phonon scatterings whereas, for sub 100nm gate lengths, the mobility is significantly degraded and almost independent with temperature. This feature is attributed to scattering by neutral defects, which are originated from source and drain process and extending over several tens of nm along the channel.

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

Abstract: We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x Ge x (x=0, 0.2, 0.25) nanowires, Si 0.7 Ge 0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W -3 dependence of ON current (I ON ) per wire. The fabricated devices exhibit higher I ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications

Abstract: This paper investigates feasible inverter configurations based on co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95 Sb platform. Based on 3-D full-quantum simulations, the considered devices feature steep subthreshold slopes and relatively high on- currents and are combined into two inverter designs. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights potential of the proposed TFET implementations to perform up to 10× and 100× faster in low operating power and low standby power environments, respectively. The comparison is conducted at low supply voltages (VDD=0.25 V) and for equal levels of static power consumption. The proposed TFET-based platform is thus expected to be a good candidate for low-voltage/low-power applications in near-future technology generations.

A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits

Abstract: This brief provides a novel voltage reference circuit that uses four optimization techniques to effectively save power dissipation: 1) All the amplifiers have been eliminated, but two important voltages are still successfully equalized without using any amplifier; 2) the clock circuits are not required in the proposed design; 3) there is no need for extra biasing circuit; and 4) all the MOS transistors are in the subthreshold region to make the power supply voltage low. Moreover, a trimming circuit has been adopted to ensure the accuracy of the reference voltage. This novel voltage reference circuit has been fabricated with the Semiconductor Manufacturing International Corporation 0.18-μm 1.8-V CMOS process. The measurement results show that the power consumption is only 19 nW, the power supply voltage is only 700 mV, the temperature coefficient is 22.11 ppm/°C under a temperature of -25 °C-+85 °C, and the line sensitivity is as good as 571 μV/V.

OFF-State Degradation of AlGaN/GaN Power HEMTs: Experimental Demonstration of Time-Dependent Drain-Source Breakdown

Abstract: This paper reports the experimental demonstration of a novel degradation mechanism of high-power AlGaN/GaN high electron mobility transistors (HEMTs), that is, time-dependent drain-source breakdown. With current-controlled breakdown measurements and constant voltage stress experiments we demonstrate that: 1) when submitted to constant voltage stress, in the OFF-state, the HEMTs can show a significant degradation; 2) the degradation process is time-dependent, and consists of a measurable increase in subthreshold drain-source leakage; this effect is ascribed to the accumulation of positive charge in proximity of the gate, consistently with previous theoretical calculations; and 3) a catastrophic (and permanent) failure is observed for long stress times, possibly due to thermal runaway or to the increase in the electric field in proximity of the localized drain-source leakage paths.

The interplay of seven subthreshold conductances controls the resting membrane potential and the oscillatory behavior of thalamocortical neurons

Abstract: The signaling properties of thalamocortical (TC) neurons depend on the diversity of ion conductance mechanisms that underlie their rich membrane behavior at subthreshold potentials. Using patch-cla...

Three-terminal nanoelectromechanical field effect transistor with abrupt subthreshold slope.

Abstract: We report the first experimental demonstration of a three-terminal nanoelectromechanical field effect transistor (NEMFET) with measurable subthreshold slope as small as 6 mV/dec at room temperature and a switching voltage window of under 2 V. The device operates by modulating drain current through a suspended nanowire channel via an insulated gate electrode, thus eliminating the need for a conducting moving electrode, and yields devices that reliably switch on/off for up to 130 cycles. Radio-frequency measurements have confirmed operation at 125 MHz. Our measurements and simulations suggest that the NEMFET design is scalable toward sub-1 V ultrahigh-frequency operation for future low-power computing systems.

Liquid and Back Gate Coupling Effect: Toward Biosensing with Lowest Detection Limit

Abstract: We employ noise spectroscopy and transconductance measurements to establish the optimal regimes of operation for our fabricated silicon nanowire field-effect transistors (Si NW FETs) sensors. A strong coupling between the liquid gate and back gate (the substrate) has been revealed and used for optimization of signal-to-noise ratio in subthreshold as well as above-threshold regimes. Increasing the sensitivity of Si NW FET sensors above the detection limit has been predicted and proven by direct experimental measurements.

Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Abstract: This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13-μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW.