scispace - formally typeset
Search or ask a question

Showing papers on "Subthreshold conduction published in 2019"



Journal ArticleDOI
15 Feb 2019-Science
TL;DR: A high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit that delivered gain near the theoretical limit at a power below 1 nanowatt and detected electrophysiological signals from the skin with a wearable device is reported.
Abstract: Overcoming the trade-offs among power consumption, fabrication cost, and signal amplification has been a long-standing issue for wearable electronics. We report a high-gain, fully inkjet-printed Schottky barrier organic thin-film transistor amplifier circuit. The transistor signal amplification efficiency is 38.2 siemens per ampere, which is near the theoretical thermionic limit, with an ultralow power consumption of 60 decibels and noise voltage of <0.3 microvolt per hertz1/2 at 100 hertz.

177 citations


Journal ArticleDOI
01 May 2019-Nature
TL;DR: It is demonstrated that Mott nanodevices retain a memory of previous resistive switching events long after the insulating resistance has recovered, and it is found that the intrinsic metastability of first-order phase transitions is the origin of this phenomenon.
Abstract: Resistive switching, a phenomenon in which the resistance of a device can be modified by applying an electric field1–5, is at the core of emerging technologies such as neuromorphic computing and resistive memories6–9. Among the different types of resistive switching, threshold firing10–14 is one of the most promising, as it may enable the implementation of artificial spiking neurons7,13,14. Threshold firing is observed in Mott insulators featuring an insulator-to-metal transition15,16, which can be triggered by applying an external voltage: the material becomes conducting (‘fires’) if a threshold voltage is exceeded7,10–12. The dynamics of this induced transition have been thoroughly studied, and its underlying mechanism and characteristic time are well documented10,12,17,18. By contrast, there is little knowledge regarding the opposite transition: the process by which the system returns to the insulating state after the voltage is removed. Here we show that Mott nanodevices retain a memory of previous resistive switching events long after the insulating resistance has recovered. We demonstrate that, although the device returns to its insulating state within 50 to 150 nanoseconds, it is possible to re-trigger the insulator-to-metal transition by using subthreshold voltages for a much longer time (up to several milliseconds). We find that the intrinsic metastability of first-order phase transitions is the origin of this phenomenon, and so it is potentially present in all Mott systems. This effect constitutes a new type of volatile memory in Mott-based devices, with potential applications in resistive memories, solid-state frequency discriminators and neuromorphic circuits. Mott materials feature scale-less relaxation dynamics after the insulator-to-metal transition that make its electric triggering dependent on recent switching events.

149 citations


Journal ArticleDOI
TL;DR: By regulating the background noise and the synaptic weight, the information of subthreshold EPSC signal is transferred accurately through the feed-forward neural network, and both time lag and fidelity between the system’s response and subth threshold EPSC signals are promoted.
Abstract: Excitatory postsynaptic current (EPSC) is a biological signal of neurons; the propagation mechanism of subthreshold EPSC signal in neural network and the effects of background noise on the propagation of the subthreshold EPSC signal are still unclear. In this paper, considering a feed-forward neural network with five layers and an external subthreshold EPSC signal imposed on the Hodgkin–Huxley neurons of first layer, the propagation and fidelity of subthreshold EPSC signal in the feed-forward neural network are studied by using the spike timing precision and power norm. It is found that the background noise in each layer is beneficial for the propagation of subthreshold EPSC signal in feed-forward neural network; there exists an optimal background noise intensity at which the propagation speed of subthreshold EPSC signal can be enhanced, and the fidelity between system’s response and subthreshold EPSC signal is preserved. The transmission of subthreshold EPSC signal is shifted from failed propagation to succeed propagation with the increasing of synaptic weight. By regulating the background noise and the synaptic weight, the information of subthreshold EPSC signal is transferred accurately through the feed-forward neural network, both time lag and fidelity between the system’s response and subthreshold EPSC signal are promoted. These results might provide a possible underlying mechanism for enhancing the subthreshold EPSC signal propagation.

71 citations


Journal ArticleDOI
TL;DR: The transient operation of a ternary inverter circuit is demonstrated for the first time and the proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielectric and encapsulating layers.
Abstract: Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H-TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H-TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (VOUT ) does not fully swing from VDD to GND . A new H-TR device structure that consists of a dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) layer stacked on a PTCDI-C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p-type off/p-type subthreshold region /NTC/ p-type on. As a result, it has a very high on/off current ratio (≈105 ) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H-TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full VDD -to-GND swing of VOUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.

70 citations


Journal ArticleDOI
TL;DR: In this article, the authors present and analyze the saturation of 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K.
Abstract: In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T

50 citations


Proceedings ArticleDOI
01 Dec 2019
TL;DR: The 3D NAND nvCIM is promising to be an energy-efficient edge computing solution for large neural networks (>100Mb weight) and can provide accuracy close to the software limitation, with reasonable tolerance to various device errors.
Abstract: We propose optimal design methods of 3D NAND Flash to achieve high-density, high-bandwidth and low-power nvCIM. By suitably engineering the device, we can produce ultra-low ON current of 2nA (mean) at saturated region instead of subthreshold region, while the OFF leakage current is much below 1pA. Such low Ion and large ON/OFF ratio provide large bandwidth to parallelly sum more than 10’000 cells together to offer high efficiency for DNN computing. The three-dimensional summation in 3D NAND also allows effective multi-bit resolution of weight without resorting to complex analog memory design. For the first time we witnessed the power of "central limit theory" in 3D NAND nvCIM, where the large number of summation averages out the noise and provides high accuracy of MAC. The effect of non-ideal cell variations, noises and shifts are studied systematically. Through adequate calibration techniques the 3D NAND nvCIM can provide accuracy close to the software limitation, with reasonable tolerance to various device errors. The 3D NAND nvCIM is promising to be an energy-efficient (TOPS/W~40) edge computing solution for large neural networks (>100Mb weight).

48 citations


Journal ArticleDOI
TL;DR: This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques, based on the proposed inverter-based elementary structure and CMFB.
Abstract: Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.

44 citations


Journal ArticleDOI
TL;DR: It is shown that the SnSe/MoS2 vdW heterostructure exhibits excellent p-n diode rectifying characteristics with low saturate current and high ON/OFF ratio over 106, demonstrating excellent electronic performance especially in the subthreshold regime.
Abstract: The minimization of the subthreshold swing (SS) in transistors is essential for low-voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal-oxide-semiconductor field-effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec-1 at room temperature). However, another type of transistor, the junction field-effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS2 van der Waals (vdW) heterostructure-based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS2 vdW heterostructure exhibits excellent p-n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS2 as the channel, the SnSe/MoS2 vdW heterostructure exhibit well-behavioured n-channel JFET characteristics with a small pinch-off voltage VP of -0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec-1 and high ON/OFF ratio over 106 , demonstrating excellent electronic performance especially in the subthreshold regime.

44 citations


Journal ArticleDOI
TL;DR: A wide input range, 4-stage threshold voltage compensated RF-to-DC power converter, designed to efficiently convert RF signals to dc voltages by applying an optimum compensation voltage produced by subthreshold auxiliary transistors is presented.
Abstract: This paper presents, a wide input range, 4-stage threshold voltage compensated RF-to-DC power converter, designed to efficiently convert RF signals to dc voltages by applying an optimum compensation voltage produced by subthreshold auxiliary transistors. The proposed optimally compensated rectifiers can achieve higher efficiency over a wider input power range compared to other threshold voltage compensation circuits where the level of the compensation is limited by the circuit structure and varies with input power. The designed rectifier is implemented in three possible ways. This proposed compensation technique can be applied to a rectifier chain with a relatively low number of stages. Designed and implemented in a 130 nm CMOS technology, the proposed rectifier exhibits a measured PCE of above 20% over the 8.5-dB input power range while driving a 1- $\text{M}\Omega $ load resistor at 896-MHz. For the same load and utilizing a minimal number of compensated rectifier stages, the proposed circuit exhibits a maximum PCE of 43% at −11 dBm for single-ended Dickson-based CMOS rectifiers. The proposed circuit demonstrates a −20.5 dBm sensitivity for 1 V output across a 1- $\text{M}\Omega $ resistive load.

43 citations


Journal ArticleDOI
TL;DR: In this paper, a sub-threshold analytical model for Dual Material Double Gate Junctionless tunnel FET (DMDG JLTFET) was developed to analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, sub- threshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation.
Abstract: A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, subthreshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation. Relating DMDG JLTFET to Junctionless MOSFETs, the results show significant reduction of Short Channel Effects (SCEs) at the drain end. The analytical model for DMDG JLTFET is effective due to the combined supremacy of uniform doping in the channel, usage of high-K gate dielectric material and work function engineering in the gate metal. The results obtained from the analytical model are simulated and validated using 2-D Sentaurus TCAD device simulator.

Journal ArticleDOI
01 Jul 2019-ACS Nano
TL;DR: The sub-threshold (or sub-bandgap) turn-on for electroluminescence is one of the most discussed, but often misinterpreted phenomena for solution-processed quantum-dot light-emitting diodes and can be readily explained using the fundamental rules of carrier injection and transport.
Abstract: The subthreshold (or sub-bandgap) turn-on for electroluminescence is one of the most discussed, but often misinterpreted, phenomena for solution-processed quantum-dot light-emitting diodes. Here, multiple techniques are applied to show that the phenomenon can be readily explained using the fundamental rules of carrier injection and transport. Evident from temperature dependent photovoltage measurements, it is found that the energy up-conversion originating from the decay of charge transfer excitons is not responsible for the subthreshold turn-on. Further analysis using electroabsorption reveals that the turn-on voltage of electroluminescence consistently correlates with the flat-band voltage of the emission layer. Under such subthreshold bias, although the device current is still limited by the depleted hole-transporting layer, field-assisted carrier injection starts to provide enough electrons and holes for detectable radiative recombination, thereby enabling distinct subthreshold turn-on.

Posted ContentDOI
23 Apr 2019-bioRxiv
TL;DR: A genetically encoded voltage indicator, SomArchon, is reported, which exhibits millisecond response times and compatibility with optogenetic control, and which increases the sensitivity, signal-to-noise ratio, and number of neurons observable, by manyfold over previous reagents.
Abstract: A longstanding goal in neuroscience has been to image membrane voltage, with high temporal precision and sensitivity, in awake behaving mammals. Here, we report a genetically encoded voltage indicator, SomArchon, which exhibits millisecond response times and compatibility with optogenetic control, and which increases the sensitivity, signal-to-noise ratio, and number of neurons observable, by manyfold over previous reagents. SomArchon only requires conventional one-photon microscopy to achieve these high performance characteristics. These improvements enable population analysis of neural activity, both at the subthreshold and spiking levels, in multiple brain regions – cortex, hippocampus, and striatum – of awake behaving mice. Using SomArchon, we detect both positive and negative responses of striatal neurons during movement, highlighting the power of voltage imaging to reveal bidirectional modulation. We also examine how the intracellular subthreshold theta oscillations of hippocampal neurons govern spike output, finding that nearby cells can exhibit highly correlated subthreshold activities, even as they generate highly divergent spiking patterns.

Journal ArticleDOI
TL;DR: This brief proposed a novel self-regulating circuit to significantly diminish the line sensitivity (LS) of reference voltage to supply voltage without using any amplifiers or passive components.
Abstract: This brief presents a CMOS voltage reference for Internet-of-Things applications, which requires ultra-low power and high insensitivity to voltage variation from ambient energy harvesting. This brief proposed a novel self-regulating circuit to significantly diminish the line sensitivity (LS) of reference voltage to supply voltage without using any amplifiers or passive components. All the transistors in this design work in subthreshold region for low voltage and low power operation. The proposed design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. The measurement results show that, the proposed circuit could provide an average reference voltage of 151 mV with a variation coefficient of 0.84 %. It achieves a LS of 0.0154 %/V when the supply voltage varies from 0.5 V to 1.8 V. The measured power supply ripple rejections at 10 Hz, 1 kHz, 100 kHz, and 1 MHz are −73.0 dB, −49.4 dB, −49.6 dB, and −49.8 dB, respectively. The average temperature coefficient is measured as 89.83 ppm/°C with a standard deviation of 12.19 ppm/°C in a temperature range from −40 °C to +125 °C. The consumed power of this design is 1 nW with a minimum supply voltage of 0.4 V at room temperature, and the active area is 0.005 mm2.

Journal ArticleDOI
TL;DR: In this article, a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field effect transistors is presented.
Abstract: This paper presents a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and does not introduce any empirical parameter. The central concept is based on the linear approximation of the channel charge density with respect to the surface potential, leading to explicit and continuous expressions for charges and current in all the regions of operation, including subthreshold. In addition, an effective circuit design methodology based on the pinchoff surface potential, the pinchoff voltage and the key concept of inversion coefficient (IC) is proposed, likewise for silicon MOSFET circuits.

Journal ArticleDOI
TL;DR: In this paper, a gate-all-around nanowire (NW) junctionless (JL) transistor was used as a sensor for low power gas sensing, specifically at low pressures (10−15−10−10 torr).
Abstract: This paper reports on the detection of hydrogen (H2) gas by utilizing a gate-all-around nanowire (NW) junctionless (JL) transistor as a sensor. The effects of temperature and pressure are considered in the transduction process through a change in gate workfunction of palladium (Pd) gate after exposure to $H_{2}$ gas. The analysis is performed through TCAD simulations, and an analytical model is developed in the subthreshold regime of device operation at a relatively low drain bias of 0.5 V. The performance of the NW JL transistor gas sensor is evaluated through the OFF-current-based sensitivity ( $S_{I}$ ) and sensitivity based on threshold voltage shift ( $S_{V}$ ). The analytical model developed for $S_{I}$ and $S_{V}$ shows a very good consistency with simulation data. The anomalous behavior of threshold voltage with temperature in the NW JL transistor under the influence of $H_{2}$ gas is analyzed in detail. This paper predominantly focuses on utilizing the NW JL transistor for low-power gas sensing, specifically at low pressures (10−15–10−10 torr), for temperatures ranging from 250 to 450 K. Insights into physical mechanisms within the device due to the transduction process are highlighted for optimum sensing.

Journal ArticleDOI
TL;DR: A wideband accurate dB-linear variable-gain amplifier is presented, which consists of three cascading gain stages with dc-offset cancellation, which achieves merits such as simple and accurate continuous dB- linear gain control, gain robustness to process and supply voltage variation and constant bandwidth at different gain settings.
Abstract: In this paper, a wideband accurate dB-linear variable-gain amplifier (VGA) is presented, which consists of three cascading gain stages with dc-offset cancellation. Based on duplicate biasing and active load techniques, this VGA achieves merits such as simple and accurate continuous dB-linear gain control, gain robustness to process and supply voltage variation and constant bandwidth at different gain settings. The dB-linear gain control is realized based on exponential current steering. The exponential conversion can be based on bipolar transistors or MOS transistors in subthreshold region. Both ways are implemented in this design for comparison purpose. With temperature compensation circuit, this VGA is insensitive to temperature variation. All gain stages of the VGA share the same biasing, exponential V-I conversion and temperature compensation circuits to reduce design complexity. This proposed VGA is fabricated in 55-nm CMOS technology with a core area of 0.033 mm2. The measurement results show the proposed VGA has a dB-linear gain-control range from −37dB to 14 dB with an error within 0.65 dB. The −3dB bandwidth of the VGA is 740 MHz and is nearly constant when the gain varies. The core VGA circuit consumes about 2.49 mW. The proposed design features wide bandwidth, small chip area, and low power consumption.

Proceedings ArticleDOI
19 May 2019
TL;DR: In this paper, the trade-off between the threshold voltage and the sub-threshold slope is discussed revealing the intricate dynamic relation between those two device metrics and the gate leakage current.
Abstract: The measured values of the threshold voltage of AlGaN/GaN high-electron-mobility transistors (HEMTs) with a p-GaN gate are generally more positive than what is expected from a classical HEMT. The transfer characteristics exhibit subthreshold slopes which are higher compared to the standard 60 mV per decade at room temperature. The higher threshold voltage values and subthreshold slopes are related to the specific structure of the p-GaN gate, consisting of two back-to-back diodes. The dominating diode—either the metal to p-GaN Schottky diode or the p-GaN/AlGaN barrier/GaN channel diode—dictates how much gate current flows, determines the subthreshold behavior, and, thus also the threshold voltage. The trade-off between the threshold voltage and the subthreshold slope is discussed revealing the intricate dynamic relation between those two device metrics and the gate leakage current.

Journal ArticleDOI
TL;DR: In this article, the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic Ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarizationvoltage predicted by Landau theory was investigated.
Abstract: We have investigated the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarization-voltage predicted by Landau theory. The dynamic FE model is applied to an FE-dielectric (FE-DE) series capacitor as well as FeFET after calibration and verification by transient measurement of an FE-HfO2 capacitor. By investigating current through the FE-DE series capacitor and the gate capacitor of FeFET, we find that incomplete screening of spontaneous polarization charge results in transient NC and sub-60 mV/dec SS. Also, it should be noted that, for FeFET, small depletion layer capacitance has an important role to cause strong depolarization effect and thus steep SS. Moreover, reverse drain induced barrier lowering happens even with this FE model. The model presented in this paper provides a reasonable interpretation for the previously reported steep SS of NC FETs.

Journal ArticleDOI
TL;DR: Li2ZnO2 is a known ion conducting oxide material, generally used as solid state electrolyte in different applications including fuel cell and Li ion battery as discussed by the authors, which has been synthesized by low cost solution processed technique and has been employed to fabricate low operating voltage metal oxide thin film transistor (TFT).

Journal ArticleDOI
Sanghoon Baek, Geun Yeol Bae1, Jimin Kwon, Kilwon Cho, Sungjune Jung 
TL;DR: In this article, organic thin-film transistor (TFT)-based pressure sensors have received huge attention for wearable electronic applications such as health monitoring and smart robotics, however, there still remain...
Abstract: Organic thin-film transistor (TFT)-based pressure sensors have received huge attention for wearable electronic applications such as health monitoring and smart robotics. However, there still remain...

Proceedings ArticleDOI
01 Jan 2019
TL;DR: In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2–300 K temperature range is studied, towards an all-operating-region mismatch model, which results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.
Abstract: Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2–300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

Journal ArticleDOI
TL;DR: This paper presents the design and the experimental results of a sub 0.5 V bulk-driven current conveyor using TSMC CMOS technology with biased transistors for low-voltage low-power operation and the measurement results confirm the proper function of the proposed circuit.
Abstract: This paper presents the design and the experimental results of a sub 0.5 V bulk-driven (BD) current conveyor (CCII) using $0.18~\mu \text{m}$ TSMC CMOS technology with a total chip area of 0.0134 mm2. All transistors are biased in the subthreshold region for low-voltage low-power operation and the input transistors are controlled from their bulk terminals for rail-to-rail input voltage range. The circuit is designed to work with voltage supply (VDD = 0.3V), which is much lower than the threshold voltage of the MOS transistor (VTH = 0.5V) while consuming 19 nW of power. The measurement results confirm the proper function of the proposed circuit.

Journal ArticleDOI
TL;DR: A CMOS floating and tunable capacitance multiplier with a very large multiplication factor using CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor.
Abstract: This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18μm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%.

Journal ArticleDOI
TL;DR: An accurate two dimensional sub-threshold modeling of Germanium based dual Halo gate stacked Triple Material Surrounding Gate (Ge-DH-GS-TM-SG) tunnel field effect transistor is proposed for the first time in this paper.

Journal ArticleDOI
TL;DR: It is shown that there are two levels of the coupling strength at which the subthreshold signal can be detected at an appropriate noise intensity and network structure and that the shorter the average path length, the better the signal detection.
Abstract: We study the effects of different coupling strengths and network topologies on signal detection in small-world neuronal networks. Research has previously revealed that the ability of detecting subthreshold signals could be significantly enhanced by appropriately fine-tuning the noise intensity. Here we show that the coupling strength and the structure of the underlying network can also lead toward enhanced signal detection. In particular, we show that there are two levels of the coupling strength at which the subthreshold signal can be detected at an appropriate noise intensity and network structure. We also show that the network structure has little impact on signal detection if the coupling is weak. On the other hand, for intermediate coupling strengths, we show that the shorter the average path length, the better the signal detection. Finally, if the coupling is strong, we show that there exists an intermediate average path length at which signal detection becomes optimal.

Journal ArticleDOI
TL;DR: In this article, two new circuit techniques are proposed for reducing the sub-threshold leakage power consumption in domino logic circuits, namely, Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DoIND (DOIND) circuits, which reduce the leakage current by 71.46 and 74.86% respectively.
Abstract: Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

Journal ArticleDOI
TL;DR: This brief models and analyzes the CMOS cross-coupled differential-drive rectifier in subthreshold operation for ambient radio frequency (RF) energy harvesting and can predict accurately the output voltage against the input RF level, number of stages, transistor size, and output load.
Abstract: This brief models and analyzes the CMOS cross-coupled differential-drive (CCDD) rectifier in subthreshold operation for ambient radio frequency (RF) energy harvesting. The developed model can predict accurately the output voltage against the input RF level, number of stages, transistor size, and output load. For validation, three CCDD rectifiers with 3, 4, and 7 stages, and dissimilar transistor sizes, were fabricated in 0.18- $ {\mu }\text{m}$ CMOS. Each rectifier was tested against different load conditions (10/30/100/500 $\text{k} \Omega $ and open circuit), and input RF levels below the threshold level of the transistor. The verified model has an accuracy of >90% up to 0 dBm input power, and 80% up to 3 dBm input power, across all denoted variations.

Journal ArticleDOI
TL;DR: This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors and achieves high-precision capacitive resolution by employing oversamplings and noise shaping.
Abstract: This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the charge-redistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74-ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 $\mu \text{W}$ from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step.

Proceedings ArticleDOI
09 Jun 2019
TL;DR: A low-power voltage reference generating 736 mV from 0 ○C to 170○C for low- power high-temperature IoT sensing systems and a BJT diode develops a process-insensitive complementary-to-absolute-tem temperature voltage, and stacked CMOS transistors compensate the temperature sensitive by adding a proportional-to theabsolute- temperature voltage.
Abstract: This paper proposes a low-power voltage reference generating 736 mV from 0 ○C to 170 ○C for low-power high-temperature IoT sensing systems. Using subthreshold current, a BJT diode develops a process-insensitive complementary-to-absolute-temperature voltage, and stacked CMOS transistors compensate the temperature sensitive by adding a proportional-to-absolute-temperature voltage. To maintain a reference voltage at high temperature, the circuit is designed considering pwell-to-deep nwell diode leakage. 76 samples from 3 different wafers, fabricated in a 180 nm process, show a ±3σ inaccuracy of 3.6% from 0 ○C to 170 ○C without any trimming. It consumes 31 pW at 27 ○C and 113 nW at 170 ○C from 0.9 V supply.